公开(公告)号：US09318222B2

公开(公告)日：2016-04-19

申请号：US14108489

申请日：2013-12-17

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Raghavendra Prasad KS ,  Harsharaj Ellur

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/04

CPC classification number: G11C29/4401 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.

Abstract translation: 内置自检（BIST）电路，用于测试集成电路上的一个或多个存储器块。 一个或多个存储器块还包括第一存储器块和第二存储器块A，内置软修复控制器（BISoR）被提供以软修复一个或多个存储器块。 配置BISoR的BIST电路配置为在执行第二个内存块的测试和软修复之前测试和软修复第一个内存块。

公开(公告)号：US09053799B2

公开(公告)日：2015-06-09

申请号：US14038306

申请日：2013-09-26

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Harsharaj Ellur

IPC: G11C29/00 ,  G11C17/16 ,  G11C17/18 ,  G11C29/44

CPC classification number: G11C29/4401 ,  G11C17/16 ,  G11C17/18 ,  G11C29/38 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/4402

Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register has a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.

Abstract translation: 集成电路（IC）中的存储器修复系统，其优化用于存储器修复的熔丝ROM。 IC包括多个存储器包装器。 每个存储器包装器包括具有熔丝寄存器和旁路寄存器的存储器块。 旁路寄存器具有指示多个存储器包装器的有缺陷的存储器包装器的旁路数据。 熔丝ROM控制器耦合到多个存储器包装器。 存储器旁路链将多个存储器封装器中的旁路寄存器与熔丝ROM控制器链接。 fuseROM控制器将旁路数据加载到内存旁路链中。 存储器数据链将多个存储器包装器中的熔丝寄存器与熔丝ROM控制器链接。 存储器数据链被重新配置为响应于加载在存储器旁路链中的旁路数据，将多个存储器包装器中的一组缺陷存储器包装器中的熔丝寄存器链接。

公开(公告)号：US09852810B2

公开(公告)日：2017-12-26

申请号：US14733524

申请日：2015-06-08

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Harsharaj Ellur

IPC: G11C29/00 ,  G11C29/44 ,  G11C17/16 ,  G11C17/18 ,  G11C29/38

CPC classification number: G11C29/4401 ,  G11C17/16 ,  G11C17/18 ,  G11C29/38 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/4402

Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.

公开(公告)号：US20150270016A1

公开(公告)日：2015-09-24

申请号：US14733524

申请日：2015-06-08

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Harsharaj Ellur

IPC: G11C29/44 ,  G11C29/38

CPC classification number: G11C29/4401 ,  G11C17/16 ,  G11C17/18 ,  G11C29/38 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/4402

Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.

公开(公告)号：US20150012786A1

公开(公告)日：2015-01-08

申请号：US14038306

申请日：2013-09-26

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Harsharaj Ellur

IPC: G11C29/12

CPC classification number: G11C29/4401 ,  G11C17/16 ,  G11C17/18 ,  G11C29/38 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/4402

Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.

Abstract translation: 集成电路（IC）中的存储器修复系统，其优化用于存储器修复的熔丝ROM。 IC包括多个存储器包装器。 每个存储器包装器包括具有熔丝寄存器和旁路寄存器的存储器块。 旁路寄存器具有指示多个存储器包装器的有缺陷的存储器包装器的旁路数据。 熔丝ROM控制器耦合到多个存储器包装器。 存储器旁路链将多个存储器封装器中的旁路寄存器与熔丝ROM控制器链接。 fuseROM控制器将旁路数据加载到内存旁路链中。 存储器数据链将多个存储器包装器中的熔丝寄存器与熔丝ROM控制器链接。 存储器数据链被重新配置为响应于加载在存储器旁路链中的旁路数据，将多个存储器包装器中的一组缺陷存储器包装器中的熔丝寄存器链接。

公开(公告)号：US20140189450A1

公开(公告)日：2014-07-03

申请号：US14108489

申请日：2013-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Raghavendra Prasad KS ,  Harsharaj Ellur

IPC: G11C29/12

CPC classification number: G11C29/4401 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.

Abstract translation: 内置自检（BIST）电路，用于测试集成电路上的一个或多个存储器块。 一个或多个存储器块还包括第一存储器块和第二存储器块A，提供内置的软修复控制器（BISoR）来软件修复所述一个或多个存储器块。 配置BISoR的BIST电路配置为在执行第二个内存块的测试和软修复之前测试和软修复第一个内存块。