公开(公告)号：US12217102B2

公开(公告)日：2025-02-04

申请号：US17551011

申请日：2021-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Varun Singh ,  Jose Luis Flores ,  Rejitha Nair ,  David Matthew Thompson

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/32

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

公开(公告)号：US20230229338A1

公开(公告)日：2023-07-20

申请号：US17900551

申请日：2022-08-31

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679

Abstract: An example device includes: converter circuitry having an output configured to couple to a first memory circuit from a plurality of memory circuits, the converter circuitry configured to: receive a first instruction formatted with a uniform protocol; and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit; logic circuitry having an input configured to couple to the first memory circuit, the logic circuitry configured to: receive a first result of the first instruction from the first memory circuit; and responsive to a second instruction, combine the first result with other results from ones of the plurality of memory circuits into an output.

公开(公告)号：US10600495B2

公开(公告)日：2020-03-24

申请号：US15891789

申请日：2018-02-08

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Sumant Kale

IPC: G11C29/38 ,  G11C29/26 ,  G11C29/36

Abstract: In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.

公开(公告)号：US20190156908A1

公开(公告)日：2019-05-23

申请号：US16192796

申请日：2018-11-15

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/16 ,  G11C29/10 ,  G11C29/12 ,  G11C29/32 ,  G01R31/3185

Abstract: A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US20240345160A1

公开(公告)日：2024-10-17

申请号：US18749823

申请日：2024-06-21

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Benjamin Niewenhuis

IPC: G01R31/317 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/31703 ,  G01R31/3177 ,  G01R31/2851 ,  G01R31/31724 ,  G01R31/318536 ,  G01R31/318547 ,  G01R31/318566 ,  G01R31/318586

Abstract: An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.

公开(公告)号：US20240170083A1

公开(公告)日：2024-05-23

申请号：US18057801

申请日：2022-11-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan

IPC: G11C29/12 ,  G11C29/18 ,  G11C29/46

CPC classification number: G11C29/1201 ,  G11C29/18 ,  G11C29/46

Abstract: An electronic circuit includes: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory, and a second data input coupled to a data output of the register; an inverter circuit having a data input coupled to the data output of the register, and a data output coupled to the data input of the memory; and a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to a data output of the comparator circuit, where the controller is configured to determine whether the memory has a fault based on the fault input of the controller.

公开(公告)号：US20170184662A1

公开(公告)日：2017-06-29

申请号：US15275694

申请日：2016-09-26

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Sumant Dinkar Kale

IPC: G01R31/28 ,  G06F11/20 ,  G11C29/12

CPC classification number: G11C29/4401 ,  G01R31/2851 ,  G06F11/2017 ,  G11C29/12 ,  G11C29/44 ,  G11C29/70 ,  G11C29/702 ,  G11C29/72 ,  G11C29/787 ,  G11C29/838 ,  G11C2029/0401

Abstract: A large-scale integrated circuit with built-in self-repair (BISR) circuitry for enabling redundancy repair for embedded memories in each of a plurality of processor cores with embedded built-in self-test (BIST) circuitry. The BISR circuitry receives and decodes BIST data from the embedded memories into fail signature data in a physical-aware form on which repair analysis can be performed. The fail signature data is reformatted into a unified repair format, such that a fuse encoder circuit can be used to encode fuse patterns in that unified repair format for a repair entity for each of the embedded memories. The fuse patterns are reconfigured into the appropriate order for storing in shadow fuse registers associated with the specific embedded memories.

公开(公告)号：US20140189450A1

公开(公告)日：2014-07-03

申请号：US14108489

申请日：2013-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Raghavendra Prasad KS ,  Harsharaj Ellur

IPC: G11C29/12

CPC classification number: G11C29/4401 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.

Abstract translation: 内置自检（BIST）电路，用于测试集成电路上的一个或多个存储器块。 一个或多个存储器块还包括第一存储器块和第二存储器块A，提供内置的软修复控制器（BISoR）来软件修复所述一个或多个存储器块。 配置BISoR的BIST电路配置为在执行第二个内存块的测试和软修复之前测试和软修复第一个内存块。

公开(公告)号：US12243603B2

公开(公告)日：2025-03-04

申请号：US18392740

申请日：2023-12-21

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/12 ,  G01R31/3185 ,  G11C29/02 ,  G11C29/10 ,  G11C29/14 ,  G11C29/16 ,  G11C29/26 ,  G11C29/32 ,  G11C29/36

Abstract: Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US20230409435A1

公开(公告)日：2023-12-21

申请号：US18239880

申请日：2023-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Ramakrishnan Venkatasubramanian ,  Varun Singh

IPC: G06F11/14 ,  H03M7/30

CPC classification number: G06F11/1448 ,  H03M7/30 ,  G06F2201/82

Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.