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Patent Agency Ranking
公开(公告)号：US11736138B2
公开(公告)日：2023-08-22
申请号：US17493943
申请日：2021-10-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Pooja Sundar , Harshavardhan Adepu , Wenjing Lu , Yeswanth Guntupalli
CPC classification number: H04B1/40 , H04B1/0075
Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.
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公开(公告)号：US11469928B2
公开(公告)日：2022-10-11
申请号：US17363855
申请日：2021-06-30
Applicant: Texas Instruments Incorporated
Inventor： Ani Xavier , Jagannathan Venkataraman , Nagalinga Swamy Basayya Aremallapur , Aviral Singhal , Arun Mohan , Rakesh Chikkanayakanahalli Manjunath , Aravind Ganesan , Harshavardhan Adepu
Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.
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公开(公告)号：US20220182266A1
公开(公告)日：2022-06-09
申请号：US17363855
申请日：2021-06-30
Applicant: Texas Instruments Incorporated
Inventor： Ani Xavier , Jagannathan Venkataraman , Nagalinga Swamy Basayya Aremallapur , Aviral Singhal , Arun Mohan , Rakesh Chikkanayakanahalli Manjunath , Aravind Ganesan , Harshavardhan Adepu
Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.
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公开(公告)号：US11177986B1
公开(公告)日：2021-11-16
申请号：US17205456
申请日：2021-03-18
Applicant: Texas Instruments Incorporated
Abstract: Adaptive equalizer circuitry including both a continuous time equalizer (CTE) and a discrete time equalizer (DTE) and a method of jointly adapting the CTE and DTE in lane adaptation. Jointly adaptation of the CTE and DTE is performed by adapting the DTE at each of a plurality of filter characteristic settings of the CTE and determining a figure of merit for signals filtered by the CTE and DTE at that condition. Adaptation of the DTE may be performed by dynamically adjusting a convergence coefficient based on a history of error gradients. After a figure of merit is determined for each of the plurality of CTE filter characteristics, a CTE filter characteristic setting is then selected based on those figure of merit values, for example at a CTE setting near a midpoint of an acceptable region of figure of merit values.
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公开(公告)号：US11171681B2
公开(公告)日：2021-11-09
申请号：US17072104
申请日：2020-10-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Pooja Sundar , Harshavardhan Adepu , Wenjing Lu , Yeswanth Guntupalli
Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.
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