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公开(公告)号：US11171681B2
公开(公告)日：2021-11-09
申请号：US17072104
申请日：2020-10-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Pooja Sundar , Harshavardhan Adepu , Wenjing Lu , Yeswanth Guntupalli
Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.
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Patent Agency Ranking
公开(公告)号：US10187071B2
公开(公告)日：2019-01-22
申请号：US15387636
申请日：2016-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Himanshu Arora , Siraj Akhtar , Lu Sun , Hamid Safiri , Wenjing Lu , Nikolaus Klemmer
Abstract: A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.
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公开(公告)号：US20170264302A1
公开(公告)日：2017-09-14
申请号：US15387636
申请日：2016-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Himanshu Arora , Siraj Akhtar , Lu Sun , Hamid Safiri , Wenjing Lu , Nikolaus Klemmer
Abstract: A multi-ladder DAC includes first and second resistor ladders, with a switch-interconnect. The switch-interconnect includes a second set of switches connected between each node of the first ladder and the top and bottom tap points of the second ladder. All other second ladder tap points are part of a loop tied to the nodes above and below each resistor through a second set of switches. Because no current flows through the switches that tie the top and bottom second-ladder tap points to the nodes of the first ladder, avoiding IRswitch error, thereby improving DNL.
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公开(公告)号：US11736138B2
公开(公告)日：2023-08-22
申请号：US17493943
申请日：2021-10-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Pooja Sundar , Harshavardhan Adepu , Wenjing Lu , Yeswanth Guntupalli
CPC classification number: H04B1/40 , H04B1/0075
Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.
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公开(公告)号：US11356125B2
公开(公告)日：2022-06-07
申请号：US16953947
申请日：2020-11-20
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Yeswanth Guntupalli , Kalyan Gudipati , Robert Clair Keller , Wenjing Lu , Jaiganesh Balakrishnan , Harsh Garg , Bragadeesh S , Raju Kharataram Chaudhari , Francesco Dantoni
Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
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公开(公告)号：US20210159924A1
公开(公告)日：2021-05-27
申请号：US16953947
申请日：2020-11-20
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Yeswanth Guntupalli , Kalyan Gudipati , Robert Clair Keller , Wenjing Lu , Jaiganesh Balakrishnan , Harsh Garg , Bragadeesh S , Raju Kharataram Chaudhari , Francesco Dantoni
Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
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