公开(公告)号：US20230299677A1

公开(公告)日：2023-09-21

申请号：US18184111

申请日：2023-03-15

Applicant: Texas Instruments Incorporated

Inventor： Hongcheng Xu ,  Michael Schlenker ,  Konrad Wagensohner

IPC: H02M3/158 ,  H02M1/00

CPC classification number: H02M3/1582 ,  H02M1/0009 ,  H02M1/0032

Abstract: A power conversion circuit includes a transconductance amplifier circuit, a current limiting circuit, and a controller. The transconductance amplifier circuit is configured to provide a first output current at a first output based on a differential between a first voltage at the first input and a second voltage at a second input. The current limiting circuit is configured to provide a second output current at the second output that is an input current at a third input limited to no greater than the first output current. The controller is configured to control first and second switches during a time period where the power conversion circuit transitions between an active mode and a skip mode.

公开(公告)号：US20250112552A1

公开(公告)日：2025-04-03

申请号：US18477721

申请日：2023-09-29

Applicant: Texas Instruments Incorporated

Inventor： Hongcheng Xu

IPC: H02M3/158 ,  G06F1/24 ,  H02M1/00 ,  H02M1/088

Abstract: A voltage monitoring circuit is configured to monitor the input voltage in a power converter and to assert a reset signal to disable operation of the power converter in response to the input voltage falling below a threshold level. The voltage monitoring circuit may include a power-on-reset (POR) block that asserts the reset signal in response to the input voltage falling below a first threshold at a first rate, and a brown-out block that asserts the reset signal in response to the input voltage falling below a second threshold at a faster second rate (e.g., the input voltage falls quickly to zero or near zero such as during a brown-out event). The brown-out block includes a backup supply voltage that maintains some positive voltage level even in the absence of the input voltage for a certain period of time and a discharge circuit designed to quickly assert the reset signal.

公开(公告)号：US20230299675A1

公开(公告)日：2023-09-21

申请号：US18170085

申请日：2023-02-16

Applicant: Texas Instruments Incorporated

Inventor： Hongcheng Xu ,  Konrad Wagensohner ,  Michael Schlenker

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M3/158 ,  H02M1/08

Abstract: Described embodiments include a circuit with a first amplifier having first and second amplifier inputs and a first amplifier output. The first amplifier input is coupled to a reference voltage terminal. The second amplifier input is coupled to a voltage feedback terminal. A second amplifier has third and fourth amplifier inputs and second and third amplifier outputs. The third amplifier input is coupled to the first amplifier output. A first switch has first and second switch terminals. The second switch terminal is coupled to the fourth amplifier input. A third amplifier has fifth and sixth amplifier inputs and a fourth amplifier output. The fifth amplifier input is coupled to the second amplifier output. The sixth amplifier input is coupled to the third amplifier output. A second switch has a third switch terminal coupled to the fourth amplifier output, and a fourth switch terminal coupled to the first amplifier output.

公开(公告)号：US20210328508A1

公开(公告)日：2021-10-21

申请号：US17361852

申请日：2021-06-29

Applicant: Texas Instruments Incorporated

Inventor： Pavol Balaz ,  Hongcheng Xu ,  Ferdinand Stettner

IPC: H02M3/07

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

公开(公告)号：US11515785B2

公开(公告)日：2022-11-29

申请号：US17361852

申请日：2021-06-29

Applicant: Texas Instruments Incorporated

Inventor： Pavol Balaz ,  Hongcheng Xu ,  Ferdinand Stettner

IPC: H02M3/07 ,  H03K19/017 ,  H03K19/20

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

公开(公告)号：US11095215B2

公开(公告)日：2021-08-17

申请号：US16690034

申请日：2019-11-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pavol Balaz ,  Hongcheng Xu ,  Ferdinand Stettner

IPC: H02M3/07 ,  H03K19/20

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.