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公开(公告)号:US11515785B2
公开(公告)日:2022-11-29
申请号:US17361852
申请日:2021-06-29
Applicant: Texas Instruments Incorporated
Inventor: Pavol Balaz , Hongcheng Xu , Ferdinand Stettner
IPC: H02M3/07 , H03K19/017 , H03K19/20
Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.
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公开(公告)号:US11095215B2
公开(公告)日:2021-08-17
申请号:US16690034
申请日:2019-11-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Pavol Balaz , Hongcheng Xu , Ferdinand Stettner
Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.
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公开(公告)号:US20240210982A1
公开(公告)日:2024-06-27
申请号:US18171006
申请日:2023-02-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Manuel Wiersch , Ferdinand Stettner
IPC: G05F3/26
CPC classification number: G05F3/262
Abstract: A circuit for controlling a discharge transistor for a power stage includes a current mirror, a first diode, and a second diode. The current mirror includes first, second, third and fourth field-effect transistors (FETs) configured to provide a fast startup signal and a startup discharge signal. The startup discharge signal is provided to a gate of the discharge transistor. The first diode is configured to limit the fast startup signal to a first maximum voltage less than the supply voltage, and the second diode is configured to limit the startup discharge signal to a second maximum voltage less than the supply voltage.
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公开(公告)号:US20210328508A1
公开(公告)日:2021-10-21
申请号:US17361852
申请日:2021-06-29
Applicant: Texas Instruments Incorporated
Inventor: Pavol Balaz , Hongcheng Xu , Ferdinand Stettner
IPC: H02M3/07
Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.
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