公开(公告)号：US11860686B2

公开(公告)日：2024-01-02

申请号：US17960383

申请日：2022-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12 ,  H03K5/00006 ,  H03K2005/00058

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US20230025885A1

公开(公告)日：2023-01-26

申请号：US17960383

申请日：2022-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/12

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US11467622B2

公开(公告)日：2022-10-11

申请号：US17182547

申请日：2021-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/12

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US20220269304A1

公开(公告)日：2022-08-25

申请号：US17182547

申请日：2021-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  G06F1/12 ,  H03K5/00

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.