公开(公告)号：US20230205256A1

公开(公告)日：2023-06-29

申请号：US17562216

申请日：2021-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Paul John Patchen ,  Ryan Alexander Smith ,  Bernd Hannes Schneider

IPC: G06F1/12 ,  H03K21/02

CPC classification number: G06F1/12 ,  H03K21/023

Abstract: An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.

公开(公告)号：US12045083B2

公开(公告)日：2024-07-23

申请号：US18240052

申请日：2023-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Per Torstein Roine

IPC: G06F1/12 ,  G06F1/06 ,  H04J3/06

CPC classification number: G06F1/12 ,  G06F1/06 ,  H04J3/0679

Abstract: A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

公开(公告)号：US11860686B2

公开(公告)日：2024-01-02

申请号：US17960383

申请日：2022-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12 ,  H03K5/00006 ,  H03K2005/00058

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US12174659B2

公开(公告)日：2024-12-24

申请号：US17824695

申请日：2022-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Gregory North ,  Robin Osa Hoel ,  Tarjei Aaberge

IPC: G06F1/10 ,  G06F1/08 ,  G06F1/12

Abstract: Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.

公开(公告)号：US11747855B2

公开(公告)日：2023-09-05

申请号：US17857837

申请日：2022-07-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Per Torstein Roine

IPC: G06F1/12 ,  G06F1/06 ,  H04J3/06

CPC classification number: G06F1/12 ,  G06F1/06 ,  H04J3/0679

Abstract: A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

公开(公告)号：US12181913B2

公开(公告)日：2024-12-31

申请号：US17562216

申请日：2021-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Paul John Patchen ,  Ryan Alexander Smith ,  Bernd Hannes Schneider

IPC: G06F1/12 ,  H03K21/02

Abstract: An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.

公开(公告)号：US20230025885A1

公开(公告)日：2023-01-26

申请号：US17960383

申请日：2022-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/12

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US11467622B2

公开(公告)日：2022-10-11

申请号：US17182547

申请日：2021-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/12

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US20220269304A1

公开(公告)日：2022-08-25

申请号：US17182547

申请日：2021-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  G06F1/12 ,  H03K5/00

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US09496024B1

公开(公告)日：2016-11-15

申请号：US14974945

申请日：2015-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivasa Raghavan Sridhara ,  Sanjeev Kumar Suman ,  Premkumar Seetharaman ,  Keshav Bhaktavatson Chintamani ,  Atul Ramakant Lele ,  Raviprakash S. Rao ,  Parvinder Kumar Rana ,  Ajith Subramonia ,  Vipul K. Singhal ,  Malav Shrikant Shah ,  Bharath Kumar Poluri

IPC: G11C5/14 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C11/413

Abstract: A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Abstract translation: 芯片上的系统（SOC）包括处理器和耦合到处理器的存储器系统。 存储器系统包括静态随机存取存储器（SRAM）存储体和存储器控制器。 SRAM库包括耦合到SRAM阵列电源的第一开关和SRAM阵列中的SRAM存储单元的晶体管的源极。 SRAM库还包括耦合到NWELL电源和SRAM存储单元的大部分晶体管的第二开关。 第二开关被配置为在SRAM阵列上电期间在第一开关闭合之前关闭。