公开(公告)号：US20240153888A1

公开(公告)日：2024-05-09

申请号：US18414003

申请日：2024-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Andrew MONTOYA ,  Salvatore Franks PAVONE

IPC: H01L23/00

CPC classification number: H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/13026 ,  H01L2924/05042 ,  H01L2924/07025

Abstract: A method includes plating a first conductive layer on a second conductive layer, the second conductive layer coupled to a device side of a semiconductor die; using a vapor deposition technique to deposit a silicon nitride layer on the first conductive layer at a pressure lower than 100 Torr; and plating a second conductive layer abutting the first conductive layer, the second conductive layer configured to receive a solder ball.

公开(公告)号：US20230065075A1

公开(公告)日：2023-03-02

申请号：US17463047

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qiao CHEN ,  Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  Jonathan Andrew MONTOYA ,  Salvatore Frank PAVONE

IPC: H01L23/00

Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

公开(公告)号：US20220352098A1

公开(公告)日：2022-11-03

申请号：US17246561

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Andrew MONTOYA ,  Salvatore Franks PAVONE

IPC: H01L23/00

Abstract: In some examples, a semiconductor package includes a semiconductor die; a passivation layer abutting a device side of the semiconductor die; a first conductive layer abutting the device side of the semiconductor die; a second conductive layer abutting the first conductive layer and the passivation layer; a silicon nitride layer abutting the second conductive layer, the silicon nitride layer having a thickness ranging from 300 Angstroms to 3000 Angstroms; and a third conductive layer coupled to the second conductive layer at a gap in the silicon nitride layer, the third conductive layer configured to receive a solder ball.