公开(公告)号：US20240363462A1

公开(公告)日：2024-10-31

申请号：US18309642

申请日：2023-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Hung-Yun LIN ,  Qiao CHEN

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05093 ,  H01L2224/13026 ,  H01L2924/15311

Abstract: In some examples, a package comprises a die having a device side with circuitry formed therein; a passivation layer abutting the device side; and first and second vias coupling to the device side and extending through the passivation layer. The package includes first and second metal layers coupled to the first and second vias, respectively, the first and second metal layers abutting the passivation layer. The package includes an insulation layer abutting the first and second metal layers and separating the first and second metal layers, the insulation layer having an orifice in vertical alignment with the second metal layer. The package includes a third metal layer coupled to the second metal layer through the orifice, the third metal layer vertically aligned with the first and second metal layers. The package comprises a conductive member coupled to the third metal layer. The package includes a mold compound covering package components.

公开(公告)号：US20250029943A1

公开(公告)日：2025-01-23

申请号：US18909550

申请日：2024-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Joseph LIU

IPC: H01L23/00

Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

公开(公告)号：US20220328438A1

公开(公告)日：2022-10-13

申请号：US17809854

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Joseph LIU

IPC: H01L23/00

Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

公开(公告)号：US20230065075A1

公开(公告)日：2023-03-02

申请号：US17463047

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qiao CHEN ,  Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  Jonathan Andrew MONTOYA ,  Salvatore Frank PAVONE

IPC: H01L23/00

Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

公开(公告)号：US20210384150A1

公开(公告)日：2021-12-09

申请号：US16950708

申请日：2020-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Joseph LIU

IPC: H01L23/00

Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

公开(公告)号：US20210193600A1

公开(公告)日：2021-06-24

申请号：US16721546

申请日：2019-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Nazila DADVAND ,  Salvatore Frank PAVONE ,  Patrick Francis THOMPSON

IPC: H01L23/00

Abstract: In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.