公开(公告)号：US10771083B2

公开(公告)日：2020-09-08

申请号：US16280233

申请日：2019-02-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Palackal Mathew

IPC: H03M1/12 ,  H03M1/10 ,  H03M1/36 ,  H03M1/18

Abstract: A system includes analog-to-digital converter (ADC) logic, wherein the ADC logic includes a stage with a dynamic comparator circuit. The ADC logic also includes a residue stage. The dynamic comparator circuit includes a preamplifier and a common mode clamp circuit for the preamplifier.

公开(公告)号：US11916567B2

公开(公告)日：2024-02-27

申请号：US17570658

申请日：2022-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy Nurani ,  Joseph Palackal Mathew ,  Prasanth K ,  Visvesvaraya Appala Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  G11C27/02

CPC classification number: H03M1/1245 ,  G11C27/02 ,  H03M1/121

Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.

公开(公告)号：US11277145B2

公开(公告)日：2022-03-15

申请号：US16850597

申请日：2020-04-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy Nurani ,  Joseph Palackal Mathew ,  Prasanth K ,  Visvesvaraya Appala Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  G11C27/02

Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.

公开(公告)号：US11569827B1

公开(公告)日：2023-01-31

申请号：US17390362

申请日：2021-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sthanunathan Ramakrishnan ,  Nithin Gopinath ,  Sai Aditya Nurani ,  Joseph Palackal Mathew ,  Nagalinga Swamy Basayya Aremallapur

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/08 ,  H03M1/10

Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.