公开(公告)号：US20200006502A1

公开(公告)日：2020-01-02

申请号：US16566924

申请日：2019-09-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jun CAI

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

Abstract: An integrated circuit includes a Laterally Diffused MOSFET (LD-MOSFET) located over a semiconductor substrate. The LD-MOSFET transistor includes a dielectric filled trench at a surface of the semiconductor substrate, and a doped region of the semiconductor substrate adjacent the dielectric-filled trench. The doped region and the dielectric-filled trench share an interface that has a terminus at the surface of the semiconductor substrate. An oxide layer is located over the semiconductor substrate, including along a surface of the doped region and along a surface of the dielectric-filled trench. The oxide layer has a first thickness over the dielectric-filled trench and a second greater thickness over the doped region.

公开(公告)号：US20190123155A1

公开(公告)日：2019-04-25

申请号：US15788216

申请日：2017-10-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jun CAI

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/408 ,  H01L21/02238 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/32 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: In accordance with at least one embodiment of the invention, a transistor comprises a semiconductor, a first drift layer, a drain region, a body region, a source region, a shallow trench isolation region, a dielectric, and a gate. The first drift layer is formed in the semiconductor and has majority carriers of a first type. The drain region is formed in the first drift layer and has majority carriers of the first type. The body region is formed in the semiconductor and has majority carriers of a second type. The source region is formed in the body region and has majority carriers of the first type. The shallow trench isolation region is formed in the first drift layer and disposed between the drain region and the body region. The dielectric is formed on the semiconductor, and the gate is formed over the dielectric and has a lift-up region.

公开(公告)号：US20190131389A1

公开(公告)日：2019-05-02

申请号：US15799783

申请日：2017-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jun CAI ,  Binghua HU

IPC: H01L29/06 ,  H01L29/866 ,  H01L21/761 ,  H01L29/868 ,  H01L29/66

CPC classification number: H01L29/0615 ,  H01L21/761 ,  H01L29/0626 ,  H01L29/66106 ,  H01L29/866 ,  H01L29/868

Abstract: In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.