公开(公告)号：US20160225672A1

公开(公告)日：2016-08-04

申请号：US15093867

申请日：2016-04-08

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. PENDHARKAR ,  Binghua HU

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66 ,  H01L21/266

CPC classification number: H01L21/0274 ,  H01L21/02694 ,  H01L21/0271 ,  H01L21/266 ,  H01L21/32 ,  H01L21/426 ,  H01L21/823493 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.

公开(公告)号：US20180175021A1

公开(公告)日：2018-06-21

申请号：US15895694

申请日：2018-02-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua HU

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8222 ,  H01L21/265 ,  H01L21/763 ,  H01L21/762 ,  H01L27/06

CPC classification number: H01L27/0259 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/762 ,  H01L21/76237 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/0623 ,  H01L29/06 ,  H01L29/0692 ,  H01L29/10 ,  H01L29/1095

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US20130157429A1

公开(公告)日：2013-06-20

申请号：US13765054

申请日：2013-02-12

Applicant: Texas Instruments Incorporated

Inventor： Pinghai HAO ,  Sameer PENDHARKAR ,  Binghua HU ,  Qingfeng WANG

IPC: H01L21/8234

CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

Abstract translation: 包含扩展漏极MOS晶体管的集成电路可以通过形成具有掩模手指的沟道区域的漂移区域注入掩模来形成，并且延伸到源极/沟道有源区，但不延伸到漏极接触有源区。 通过暴露的指状物注入的掺杂剂在掩模指下面的衬底中形成横向掺杂条纹。 栅极下方的漂移区域的平均掺杂密度比漏极接触有效面积处的漂移区域的平均掺杂密度小至少25％。 在一个实施例中，掺杂剂横向漫射以形成连续漂移区域。 在另一个实施例中，横向掺杂条纹之间的衬底材料与横向掺杂条纹保持相反的导电类型。

公开(公告)号：US20150214096A1

公开(公告)日：2015-07-30

申请号：US14682823

申请日：2015-04-09

Applicant: Texas Instruments Incorporated

Inventor： Binghua HU ,  Sameer PENDHARKAR ,  Guru MATHUR ,  Takehito TAMURA

IPC: H01L21/762 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/265 ,  H01L21/283

CPC classification number: H01L21/76224 ,  H01L21/02109 ,  H01L21/265 ,  H01L21/283 ,  H01L21/32055 ,  H01L21/76232 ,  H01L29/0619

Abstract: The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.

Abstract translation: 通过形成重掺杂沉降片位于已形成于半导体材料中的多个紧密间隔的沟槽隔离结构之间，大大减小了重掺杂沉降片的宽度。 在进入期间，紧密间隔的沟槽隔离结构显着限制了横向扩散。

公开(公告)号：US20200066710A1

公开(公告)日：2020-02-27

申请号：US16666563

申请日：2019-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua HU

IPC: H01L27/02 ,  H01L21/265 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/763

Abstract: An integrated circuit (IC) includes a semiconductor substrate in which a plurality of spaced-apart deep trench (DT) structures are formed. The IC further includes a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures. Each of the DEEPN diffusion regions merges with at least one neighboring DEEPN diffusion region that surrounds at least one neighboring DT structure. The merged DEEPN diffusion regions may partially isolate two electronic devices, e.g. ESD devices.

公开(公告)号：US20190304786A1

公开(公告)日：2019-10-03

申请号：US15944550

申请日：2018-04-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas ALI ,  Binghua HU ,  Stephanie L. HILBUN ,  Scott William JESSEN ,  Ronald CHIN ,  Jarvis Benjamin JACOBS

IPC: H01L21/266 ,  H01L29/66

Abstract: A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

公开(公告)号：US20190131389A1

公开(公告)日：2019-05-02

申请号：US15799783

申请日：2017-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jun CAI ,  Binghua HU

IPC: H01L29/06 ,  H01L29/866 ,  H01L21/761 ,  H01L29/868 ,  H01L29/66

CPC classification number: H01L29/0615 ,  H01L21/761 ,  H01L29/0626 ,  H01L29/66106 ,  H01L29/866 ,  H01L29/868

Abstract: In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

公开(公告)号：US20180151722A1

公开(公告)日：2018-05-31

申请号：US15865028

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Binghua HU ,  James Robert TODD

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L29/10 ,  H01L21/265 ,  H01L29/08 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.

公开(公告)号：US20150187658A1

公开(公告)日：2015-07-02

申请号：US14575457

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. PENDHARKAR ,  Binghua HU

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66 ,  H01L21/266

CPC classification number: H01L21/0274 ,  H01L21/02694 ,  H01L21/0271 ,  H01L21/266 ,  H01L21/32 ,  H01L21/426 ,  H01L21/823493 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.

Abstract translation: 一种使用一个光致抗蚀剂图案和注入工艺步骤在晶片的表面处形成至少两种不同掺杂水平的工艺。 开发抗蚀剂层（但不烘烤）以形成第一抗蚀剂几何形状和多个亚光刻抗蚀剂几何形状。 烘烤抗蚀剂层，使得亚光刻抗蚀剂几何形状回流到具有小于第一抗蚀剂几何形状的厚度的连续的第二抗蚀剂几何形状。 高能量注入通过第二抗蚀剂几何体注入掺杂剂，但不通过第一抗蚀剂几何形状。 低能量植入物被第一和第二抗蚀剂几何形状阻挡。