公开(公告)号：US09240404B2

公开(公告)日：2016-01-19

申请号：US14492406

申请日：2014-09-22

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Ki-Don Lee ,  Stanley Seungchul Song

IPC: H01L27/06 ,  H01L29/66 ,  H01L49/02 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/66575 ,  H01L29/7833

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract translation: 可以在替代栅极高k金属栅极金属氧化物半导体（MOS）技术工艺流程中形成的集成电路中的嵌入式电阻器结构。 通过在期望的位置移除浅沟槽隔离结构或通过硅蚀刻，将沟槽蚀刻到衬底中来形成结构。 伪栅极多晶硅层的沉积用多晶硅填充沟槽; 电阻多晶硅部分被硬掩模层保护以防止伪栅极多晶硅去除。 电阻器多晶硅可以在源极/漏极注入期间被掺杂，并且可以使其接触位置硅化物包覆而不降低金属栅电极。

公开(公告)号：US08865542B2

公开(公告)日：2014-10-21

申请号：US13736558

申请日：2013-01-08

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Ki-Don Lee ,  Stanley Seungchul Song

IPC: H01L21/8244 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/66575 ,  H01L29/7833

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract translation: 可以在替代栅极高k金属栅极金属氧化物半导体（MOS）技术工艺流程中形成的集成电路中的嵌入式电阻器结构。 通过在期望的位置移除浅沟槽隔离结构或通过硅蚀刻，将沟槽蚀刻到衬底中来形成结构。 伪栅极多晶硅层的沉积用多晶硅填充沟槽; 电阻多晶硅部分被硬掩模层保护以防止伪栅极多晶硅去除。 电阻器多晶硅可以在源极/漏极注入期间被掺杂，并且可以使其接触位置硅化物包覆而不降低金属栅电极。

公开(公告)号：US20140183657A1

公开(公告)日：2014-07-03

申请号：US13736558

申请日：2013-01-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kwan-Yong Lim ,  Ki-Don Lee ,  Stanley Seungchul Song

IPC: H01L29/66 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/66575 ,  H01L29/7833

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract translation: 可以在替代栅极高k金属栅极金属氧化物半导体（MOS）技术工艺流程中形成的集成电路中的嵌入式电阻器结构。 通过在期望的位置移除浅沟槽隔离结构或通过硅蚀刻，将沟槽蚀刻到衬底中来形成结构。 伪栅极多晶硅层的沉积用多晶硅填充沟槽; 电阻多晶硅部分被硬掩模层保护以防止伪栅极多晶硅去除。 电阻器多晶硅可以在源极/漏极注入期间被掺杂，并且可以使其接触位置硅化物包覆而不降低金属栅电极。