公开(公告)号：US09508601B2

公开(公告)日：2016-11-29

申请号：US14563062

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  James Walter Blatchford ,  Shashank S. Ekbote ,  Younsung Choi

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Abstract translation: 在MOS间隔填充有二氧化硅的间隙填料，形成与MOS晶体管邻接的MOS晶体管和与MOS晶体管相邻的场氧化物上的栅极结构和外延源极/漏极与场氧化物之间的间隙的集成电路。 在暴露的外延源极/漏极区上形成金属硅化物。 在集成电路上形成CESL，并且在CESL上形成PMD层。 通过PMD层和CESL形成接触以与外延源极/漏极区上的金属硅化物形成电连接。

公开(公告)号：US20160172443A1

公开(公告)日：2016-06-16

申请号：US14967199

申请日：2015-12-11

Applicant: Texas Instruments Incorporated

Inventor： Younsung Choi ,  Kwan-Yong Lim ,  Seung-Chul Song ,  Song Zhao

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L29/4916 ,  H01L29/66575 ,  H01L29/78

Abstract: A method for tuning a threshold voltage of a semiconductor device includes implanting at least one dopant in a semiconductor substrate at an angle to form a source region and/or a drain region of a transistor. The angle is oblique to a surface of the substrate. Implanting the at least one dopant at the angle alters a flat-band voltage of the transistor and shifts the threshold voltage of the transistor. The at least one dopant or at least one additional dopant can be implanted in a gate electrical contact of the transistor. Implanting the at least one dopant at the oblique angle can change an electrostatic potential of a gate electrical contact of the transistor compared to implanting the at least one dopant at a non-oblique angle, and the change in the electrostatic potential of the gate electrical contact can shift the threshold voltage of the transistor.

Abstract translation: 用于调整半导体器件的阈值电压的方法包括以一定角度在半导体衬底中注入至少一种掺杂剂以形成晶体管的源极区和/或漏极区。 该角度与衬底的表面倾斜。 以角度植入至少一种掺杂剂会改变晶体管的平带电压并使晶体管的阈值电压发生偏移。 可以将至少一种掺杂剂或至少一种附加掺杂剂注入到晶体管的栅极电接触中。 以倾斜角度植入所述至少一种掺杂剂可以改变晶体管的栅极电接触的静电电位，以便以非倾斜角度注入至少一种掺杂剂，并且栅极电接触的静电电位的变化 可以移动晶体管的阈值电压。

公开(公告)号：US09178038B2

公开(公告)日：2015-11-03

申请号：US14609051

申请日：2015-01-29

Applicant: Texas Instruments Incorporated

Inventor： Seung-Chul Song ,  James W. Blatchford ,  Kwan-Yong Lim

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.

Abstract translation: 凸起的源极/漏极MOS晶体管形成在利用第一侧壁间隔物的过程中，当注入半导体区域以形成晶体管的重掺杂源极区域和重掺杂漏极区域时，以及第二不同侧壁间隔物，当外延 生长晶体管的升高的源极区域和升高的漏极区域。

公开(公告)号：US08865549B2

公开(公告)日：2014-10-21

申请号：US13707865

申请日：2012-12-07

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。

公开(公告)号：US09812452B2

公开(公告)日：2017-11-07

申请号：US15336248

申请日：2016-10-27

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  James Walter Blatchford ,  Shashank S. Ekbote ,  Younsung Choi

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/8234 ,  H01L23/535

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

公开(公告)号：US09406769B2

公开(公告)日：2016-08-02

申请号：US14875343

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. Ekbote ,  Kwan-Yong Lim ,  Ebenezer Eshun ,  Youn Sung Choi

IPC: H01L29/08 ,  H01L29/45 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/161 ,  H01L21/28 ,  H01L29/78 ,  H01L29/165 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

公开(公告)号：US09245975B2

公开(公告)日：2016-01-26

申请号：US14487663

申请日：2014-09-16

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/04

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。

公开(公告)号：US09093298B2

公开(公告)日：2015-07-28

申请号：US13972973

申请日：2013-08-22

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. Ekbote ,  Kwan-Yong Lim ,  Ebenezer Eshun ,  Youn Sung Choi

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

公开(公告)号：US08865542B2

公开(公告)日：2014-10-21

申请号：US13736558

申请日：2013-01-08

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Ki-Don Lee ,  Stanley Seungchul Song

IPC: H01L21/8244 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/66575 ,  H01L29/7833

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract translation: 可以在替代栅极高k金属栅极金属氧化物半导体（MOS）技术工艺流程中形成的集成电路中的嵌入式电阻器结构。 通过在期望的位置移除浅沟槽隔离结构或通过硅蚀刻，将沟槽蚀刻到衬底中来形成结构。 伪栅极多晶硅层的沉积用多晶硅填充沟槽; 电阻多晶硅部分被硬掩模层保护以防止伪栅极多晶硅去除。 电阻器多晶硅可以在源极/漏极注入期间被掺杂，并且可以使其接触位置硅化物包覆而不降低金属栅电极。

公开(公告)号：US20140183657A1

公开(公告)日：2014-07-03

申请号：US13736558

申请日：2013-01-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kwan-Yong Lim ,  Ki-Don Lee ,  Stanley Seungchul Song

IPC: H01L29/66 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/66575 ,  H01L29/7833

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract translation: 可以在替代栅极高k金属栅极金属氧化物半导体（MOS）技术工艺流程中形成的集成电路中的嵌入式电阻器结构。 通过在期望的位置移除浅沟槽隔离结构或通过硅蚀刻，将沟槽蚀刻到衬底中来形成结构。 伪栅极多晶硅层的沉积用多晶硅填充沟槽; 电阻多晶硅部分被硬掩模层保护以防止伪栅极多晶硅去除。 电阻器多晶硅可以在源极/漏极注入期间被掺杂，并且可以使其接触位置硅化物包覆而不降低金属栅电极。