公开(公告)号：US08865549B2

公开(公告)日：2014-10-21

申请号：US13707865

申请日：2012-12-07

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。

公开(公告)号：US09245975B2

公开(公告)日：2016-01-26

申请号：US14487663

申请日：2014-09-16

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/04

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。

公开(公告)号：US08865542B2

公开(公告)日：2014-10-21

申请号：US13736558

申请日：2013-01-08

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Ki-Don Lee ,  Stanley Seungchul Song

IPC: H01L21/8244 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/66575 ,  H01L29/7833

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract translation: 可以在替代栅极高k金属栅极金属氧化物半导体（MOS）技术工艺流程中形成的集成电路中的嵌入式电阻器结构。 通过在期望的位置移除浅沟槽隔离结构或通过硅蚀刻，将沟槽蚀刻到衬底中来形成结构。 伪栅极多晶硅层的沉积用多晶硅填充沟槽; 电阻多晶硅部分被硬掩模层保护以防止伪栅极多晶硅去除。 电阻器多晶硅可以在源极/漏极注入期间被掺杂，并且可以使其接触位置硅化物包覆而不降低金属栅电极。

公开(公告)号：US20140183657A1

公开(公告)日：2014-07-03

申请号：US13736558

申请日：2013-01-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kwan-Yong Lim ,  Ki-Don Lee ,  Stanley Seungchul Song

IPC: H01L29/66 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/66575 ,  H01L29/7833

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract translation: 可以在替代栅极高k金属栅极金属氧化物半导体（MOS）技术工艺流程中形成的集成电路中的嵌入式电阻器结构。 通过在期望的位置移除浅沟槽隔离结构或通过硅蚀刻，将沟槽蚀刻到衬底中来形成结构。 伪栅极多晶硅层的沉积用多晶硅填充沟槽; 电阻多晶硅部分被硬掩模层保护以防止伪栅极多晶硅去除。 电阻器多晶硅可以在源极/漏极注入期间被掺杂，并且可以使其接触位置硅化物包覆而不降低金属栅电极。

公开(公告)号：US20140159142A1

公开(公告)日：2014-06-12

申请号：US13707865

申请日：2012-12-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。

公开(公告)号：US09240404B2

公开(公告)日：2016-01-19

申请号：US14492406

申请日：2014-09-22

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Ki-Don Lee ,  Stanley Seungchul Song

IPC: H01L27/06 ,  H01L29/66 ,  H01L49/02 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/66575 ,  H01L29/7833

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract translation: 可以在替代栅极高k金属栅极金属氧化物半导体（MOS）技术工艺流程中形成的集成电路中的嵌入式电阻器结构。 通过在期望的位置移除浅沟槽隔离结构或通过硅蚀刻，将沟槽蚀刻到衬底中来形成结构。 伪栅极多晶硅层的沉积用多晶硅填充沟槽; 电阻多晶硅部分被硬掩模层保护以防止伪栅极多晶硅去除。 电阻器多晶硅可以在源极/漏极注入期间被掺杂，并且可以使其接触位置硅化物包覆而不降低金属栅电极。

公开(公告)号：US20150037952A1

公开(公告)日：2015-02-05

申请号：US14487663

申请日：2014-09-16

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。