公开(公告)号：US11349492B2

公开(公告)日：2022-05-31

申请号：US17112095

申请日：2020-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Minkle Eldho Paul ,  Laxmi Vivek Tripurari ,  Amal Kumar Kundu

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/10 ,  H03M1/06 ,  G11C27/02 ,  H03M1/00

Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

公开(公告)号：US10819294B1

公开(公告)日：2020-10-27

申请号：US16574231

申请日：2019-09-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Laxmi Vivek Tripurari ,  Anand Subramanian

IPC: H03F1/56 ,  H04R3/04 ,  H04R3/00

Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.

公开(公告)号：US10886933B1

公开(公告)日：2021-01-05

申请号：US16656913

申请日：2019-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Minkle Eldho Paul ,  Laxmi Vivek Tripurari ,  Amal Kumar Kundu

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/10 ,  H03M1/06 ,  G11C27/02 ,  H03M1/00

Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

公开(公告)号：US11527999B2

公开(公告)日：2022-12-13

申请号：US17027093

申请日：2020-09-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Laxmi Vivek Tripurari ,  Anand Subramanian

IPC: H03F1/56 ,  H04R3/04 ,  H04R3/00

Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.