公开(公告)号：US20190004967A1

公开(公告)日：2019-01-03

申请号：US15991241

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/1081 ,  G06F13/18 ,  H03K21/00 ,  G06F1/32 ,  G06F7/483 ,  G06F9/30 ,  G06F11/10 ,  H03M13/35 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/16 ,  H03M13/29 ,  H03K19/00 ,  G06F12/02 ,  G06F13/364

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：USRE46193E1

公开(公告)日：2016-11-01

申请号：US14303262

申请日：2014-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Lewis Nardini ,  Jose Luis Flores ,  Abhijeet Chachad ,  Raguram Damodaran ,  Joseph R. M. Zbiciak ,  Gary Swoboda

IPC: G06F1/32

Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

Abstract translation: 嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。 要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。 因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

公开(公告)号：US20150269090A1

公开(公告)日：2015-09-24

申请号：US14728541

申请日：2015-06-02

Applicant: Texas Instruments Incorporated

Inventor： Jonathan (Son) Hung Tran ,  Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.

Abstract translation: 本发明将DMA写入优化为直接可寻址的二级存储器，该存储器缓存在一级，并且该行是有效和脏的。 当二级控制器检测到一级线路有效且脏一级时，二级存储器不需要更新其数据副本。 一级记忆将在将来的时候用受害者回写替代第二级副本。 因此，二级内存不需要存储写入副本。 这将DMA写入次数限制在二级可直接寻址的存储器中，从而提高性能并最大限度地减少动态功耗。 这也释放了其他主/请求者的二级内存。

公开(公告)号：US20140122810A1

公开(公告)日：2014-05-01

申请号：US13660003

申请日：2012-10-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Raguram Damodaran

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream.

Abstract translation: 通过将块无效操作与正常的CPU访问重叠来消除多CPU环境中多个重叠块无效操作的延迟的方法，从而使延迟透明。 执行块无效操作的高速缓存控制器将多个重叠的请求合并到并行流中以消除执行延迟。 缓存操作其他块无效，如块写回或块写回无效也可以合并到执行流中。

公开(公告)号：US11537532B2

公开(公告)日：2022-12-27

申请号：US16916239

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F12/1081 ,  G06F7/483 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815 ,  G06F13/364

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：US09965395B2

公开(公告)日：2018-05-08

申请号：US14874842

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Joseph Raymond Michael Zbiciak ,  Naveen Bhoria

IPC: G06F12/00 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/0862

CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/6022 ,  G06F2212/70

Abstract: The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

公开(公告)号：US09575901B2

公开(公告)日：2017-02-21

申请号：US14884138

申请日：2015-10-15

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/10 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/32 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/08 ,  G06F13/364

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.

Abstract translation: 本发明是具有多个条目的存储器属性寄存器的缓存系统。 每个条目存储对应的存储器地址范围的直写或回写指示。 在对高速缓存数据进行写入时，高速缓存会针对相应的地址范围查询存储器属性寄存器。 写入写入区域的地址写入将始终更新内存层次结构的所有级别。 写入标记为回写的区域中的地址只能更新可以为写入服务的第一个缓存级别。 存储器属性寄存器优选地是由中央处理单元可写的存储器映射控制寄存器。

公开(公告)号：US09390011B2

公开(公告)日：2016-07-12

申请号：US14875801

申请日：2015-10-06

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F13/28

CPC classification number: G06F12/0808 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/62 ,  Y02D10/13

Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation is treated as a cache miss to ensure that the requesting CPU will receive valid data.

公开(公告)号：US20160034396A1

公开(公告)日：2016-02-04

申请号：US14884138

申请日：2015-10-15

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson

IPC: G06F12/08

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.

Abstract translation: 本发明是具有多个条目的存储器属性寄存器的缓存系统。 每个条目存储对应的存储器地址范围的直写或回写指示。 在对高速缓存数据进行写入时，高速缓存会针对相应的地址范围查询存储器属性寄存器。 写入写入区域的地址写入将始终更新内存层次结构的所有级别。 写入标记为回写的区域中的地址只能更新可以为写入服务的第一个缓存级别。 存储器属性寄存器优选地是由中央处理单元可写的存储器映射控制寄存器。

公开(公告)号：US08977915B2

公开(公告)日：2015-03-10

申请号：US13709247

申请日：2012-12-10

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G11C29/22 ,  G11C29/16 ,  G11C29/54 ,  G11C11/41 ,  G11C29/04

CPC classification number: G11C29/16 ,  G11C11/41 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.

Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 在分布式数据记录架构中执行测试数据比较，以最小化分布式数据记录器和pBIST之间的互连数量。