公开(公告)号：US10581416B2

公开(公告)日：2020-03-03

申请号：US16361154

申请日：2019-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Junhong Zhang ,  Angelo Pereira ,  Pinar Korkmaz ,  Sujan Manohar ,  Michael Munroe

IPC: H03K4/06 ,  H03L7/00 ,  H02M3/158 ,  H03K5/135 ,  G06F1/12 ,  H03K3/027

Abstract: Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.

公开(公告)号：US10367484B2

公开(公告)日：2019-07-30

申请号：US15222860

申请日：2016-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mingyue Zhao ,  Jiwei Fan ,  Michael Munroe

IPC: H03K4/48 ,  H03L7/00 ,  H02M3/158 ,  H03K4/502 ,  H03K3/3562

Abstract: A phase generation circuit is disclosed. The circuit includes a ramp generation circuit arranged to generate a ramp signal in synchronization with a synchronization clock signal. A phase selection circuit generates a reference signal in response to a phase selection signal. A comparator has a first input terminal coupled to receive the ramp signal and a second input terminal coupled to receive the reference signal. The comparator produces a phase clock signal at an output terminal.

公开(公告)号：US20180034450A1

公开(公告)日：2018-02-01

申请号：US15222860

申请日：2016-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mingyue Zhao ,  Jiwei Fan ,  Michael Munroe

IPC: H03K4/48 ,  H03K3/3562 ,  H02M3/158 ,  H03L7/00

CPC classification number: H03K4/48 ,  H02M3/1584 ,  H02M2003/1586 ,  H03K3/3562 ,  H03K4/502 ,  H03L7/00

Abstract: A phase generation circuit is disclosed. The circuit includes a ramp generation circuit arranged to generate a ramp signal in synchronization with a synchronization clock signal. A phase selection circuit generates a reference signal in response to a phase selection signal. A comparator has a first input terminal coupled to receive the ramp signal and a second input terminal coupled to receive the reference signal. The comparator produces a phase clock signal at an output terminal.