公开(公告)号：US11631454B2

公开(公告)日：2023-04-18

申请号：US16744412

申请日：2020-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Sudesh Chandra Srivastava ,  Mohammed Nabeel

IPC: G11C11/418 ,  G06F13/16 ,  G06F13/40 ,  G11C11/419 ,  G06F11/10 ,  G11C11/50

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

公开(公告)号：US20200152261A1

公开(公告)日：2020-05-14

申请号：US16744412

申请日：2020-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Sudesh Chandra Srivastava ,  Mohammed Nabeel

IPC: G11C11/418 ,  G06F11/10 ,  G11C11/419 ,  G06F13/40 ,  G06F13/16

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

公开(公告)号：US10559351B2

公开(公告)日：2020-02-11

申请号：US15437253

申请日：2017-02-20

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Sudesh Chandra Srivastava ,  Mohammed Nabeel

IPC: G11C11/418 ,  G06F13/16 ,  G06F13/40 ,  G11C11/42

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

公开(公告)号：US20180239530A1

公开(公告)日：2018-08-23

申请号：US15437253

申请日：2017-02-20

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Sudesh Chandra Srivastava ,  Mohammed Nabeel

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G11C11/418 ,  G06F11/10

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

公开(公告)号：US09287876B1

公开(公告)日：2016-03-15

申请号：US14623364

申请日：2015-02-16

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Mohammed Nabeel

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17724 ,  H03K19/1737 ,  H03K19/17736

Abstract: A device includes a plurality of functional logic blocks, a cascaded arrangement of multiplexers and a digital counter. Each of the plurality of functional logic blocks outputs a signals corresponding to nodes to be tested therein. The cascaded arrangement of multiplexers are arranged such that any of the outputs from any of the plurality of functional logic blocks may be selected for output. The digital counter is operable to control the cascaded arrangement of multiplexers so as to output signals from the functional logic blocks based on a counted signal.

Abstract translation: 一种设备包括多个功能逻辑块，多路复用器的级联布置和数字计数器。 多个功能逻辑块中的每一个输出与其中要测试的节点对应的信号。 多路复用器的级联布置被布置成使得可以选择多个功能逻辑块中的任一个的任何输出用于输出。 数字计数器可操作以控制多路复用器的级联布置，以便基于计数的信号从功能逻辑块输出信号。