公开(公告)号：US20220342634A1

公开(公告)日：2022-10-27

申请号：US17241753

申请日：2021-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arnab Khawas ,  Nandini Bollam ,  Badarish Mohan Subbannavar

IPC: G06F7/501 ,  H03K17/687

Abstract: Examples of compact, high performance full adder circuits and methods of forming and operating the same are provided. In an example, a full adder comprises a first stage, a second stage and a third stage. The first stage has a first output at which a first reused signal is generated and a second output at which a second reused signal is generated. The second stage has a first reused signal input to which the first reused signal is applied, a second reused signal input to which the second reused signal is applied, and a sum output at which a sum signal is generated. The third stage has a third reused signal input to which the first reused signal is applied, a fourth reused signal input to which the second reused signal is applied, and a carry-out output at which a carry-out signal is generated. In some examples, the first stage includes a transistor stack and an inverter that share a transistor.