公开(公告)号：US20250105809A1

公开(公告)日：2025-03-27

申请号：US18428170

申请日：2024-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hua Shao ,  Paul Damitio ,  Bharath Karthik Vasan ,  Joel Martin Halbert

IPC: H03F3/45 ,  H03F1/30 ,  H03K17/30

Abstract: An amplifier includes first through sixth transistors. The first transistor is of a first polarity type and has a control terminal and first and second terminals. The second transistor is of a second polarity type and has a control terminal and first and second terminals. The third transistor is of the first polarity type and has a control terminal and first and second terminals. The second terminal of the third transistor is coupled to the first terminal of the second transistor. The fourth transistor is of the second polarity type and has a control terminal and first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the second transistor. The fifth transistor has a control terminal coupled to the control terminal of the third transistor. A sixth transistor has a control terminal coupled to the control terminal of the fourth transistor.

公开(公告)号：US20250105800A1

公开(公告)日：2025-03-27

申请号：US18759086

申请日：2024-06-28

Applicant: Texas Instruments Incorporated

Inventor： Hua Shao ,  Paul Damitio ,  Bharath Karthik Vasan ,  Joel M. Halbert

IPC: H03F3/04

Abstract: An example apparatus includes: first buffer circuitry having a first terminal and a second terminal; second buffer circuitry having a first terminal and a second terminal; third buffer circuitry having a first terminal and a second terminal, the first terminal of the third buffer circuitry coupled to the first terminal of the second buffer circuitry; a first transistor having a first terminal, a second terminal and a control terminal, the first terminal of the first transistor coupled to the first terminal of the first buffer circuitry, the control terminal of the first transistor coupled to the second terminal of the second buffer circuitry; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the second terminal of the first buffer circuitry.