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    AMPLIFIER WITH PRE-DRIVER HAVING CROSS-COUPLED TRANSISTORS
    1.
    发明申请
    AMPLIFIER WITH PRE-DRIVER HAVING CROSS-COUPLED TRANSISTORS 有权

    公开(公告)号：US20250105809A1

    公开(公告)日：2025-03-27

    申请号：US18428170

    申请日：2024-01-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Hua Shao ,  Paul Damitio ,  Bharath Karthik Vasan ,  Joel Martin Halbert

    IPC: H03F3/45 ,  H03F1/30 ,  H03K17/30

    Abstract: An amplifier includes first through sixth transistors. The first transistor is of a first polarity type and has a control terminal and first and second terminals. The second transistor is of a second polarity type and has a control terminal and first and second terminals. The third transistor is of the first polarity type and has a control terminal and first and second terminals. The second terminal of the third transistor is coupled to the first terminal of the second transistor. The fourth transistor is of the second polarity type and has a control terminal and first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the second transistor. The fifth transistor has a control terminal coupled to the control terminal of the third transistor. A sixth transistor has a control terminal coupled to the control terminal of the fourth transistor.

    Fully-differential amplifier with input common-mode voltage control
    2.
    发明授权
    Fully-differential amplifier with input common-mode voltage control 有权

    公开(公告)号：US11990879B2

    公开(公告)日：2024-05-21

    申请号：US17316775

    申请日：2021-05-11

    Applicant: Texas Instruments Incorporated

    Inventor： Joel Martin Halbert ,  Xiyao Zhang

    IPC: H03F3/45

    CPC classification number: H03F3/45475 ,  H03F2200/129

    Abstract: A fully-differential amplifier (FDA) includes a core differential amplifier and a common-mode input voltage control circuit. The core differential amplifier includes differential inputs. The common-mode input voltage control circuit is coupled to the differential inputs. The common-mode input voltage control circuit is configured to generate an error signal as a difference of an input common mode voltage at the differential inputs and a target common mode input voltage (VICM); and to adjust the input common mode voltage to the VICM based on the error signal.

    Control of base currents for output driver transistors in amplifiers
    3.
    发明授权
    Control of base currents for output driver transistors in amplifiers 有权

    公开(公告)号：US11764740B2

    公开(公告)日：2023-09-19

    申请号：US17462930

    申请日：2021-08-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Tyler James Archer ,  Joel Martin Halbert ,  Bharath Karthik Vasan

    IPC: H03F3/04 ,  H03F3/26

    CPC classification number: H03F3/04

    Abstract: Examples of amplifiers accurately generate control currents for control terminals of output drivers using current-replication transistors and current mirrors. An input terminal of a first current mirror is coupled to the control terminal of a first current-replication transistor, and an input terminal of a second current mirror is coupled to the control terminal of a second current-replication transistor. The output terminals of the first and second current mirrors are coupled to the control terminals of first and second output drivers, respectively. First and second intermediate currents indicative of first and second currents flowing to the first and second output driver elements, respectively, are generated. Using the first and second current mirrors, first and second control currents are generated to control the first and second output driver elements, respectively, by scaling the first and second intermediate currents according to the gain factors of the current mirrors.

    CONTROL OF INPUT BIAS CURRENT MODULATION IN AMPLIFIERS
    5.
    发明申请
    CONTROL OF INPUT BIAS CURRENT MODULATION IN AMPLIFIERS 有权

    公开(公告)号：US20230060318A1

    公开(公告)日：2023-03-02

    申请号：US17462868

    申请日：2021-08-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Tyler James Archer ,  Paul Gerard Damitio ,  Joel Martin Halbert ,  Bharath Karthik Vasan

    IPC: H03F3/04

    Abstract: Examples of amplifiers use current-replication transistors and a separation circuit coupled to such transistors to separate error current components from other current components in a pre-driver of an amplifier. In response to driving the current-replication transistors with the separated error current components, replica base current components that approximate error-modulation components of the pre-driver base currents are generated. Replica-current subtraction circuitry coupled to the current-replication transistors then subtract the replica base current components from the pre-driver base currents, affecting cancellation of the error-modulation components of the pre-driver base currents.

    Control of input bias current modulation in amplifiers
    8.
    发明授权
    Control of input bias current modulation in amplifiers 有权

    公开(公告)号：US11722104B2

    公开(公告)日：2023-08-08

    申请号：US17462868

    申请日：2021-08-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Tyler James Archer ,  Paul Gerard Damitio ,  Joel Martin Halbert ,  Bharath Karthik Vasan

    IPC: H03F3/04 ,  H03F3/26

    CPC classification number: H03F3/04

    Abstract: Examples of amplifiers use current-replication transistors and a separation circuit coupled to such transistors to separate error current components from other current components in a pre-driver of an amplifier. In response to driving the current-replication transistors with the separated error current components, replica base current components that approximate error-modulation components of the pre-driver base currents are generated. Replica-current subtraction circuitry coupled to the current-replication transistors then subtract the replica base current components from the pre-driver base currents, affecting cancellation of the error-modulation components of the pre-driver base currents.

    Integrated JFET structure with implanted backgate
    9.
    发明授权
    Integrated JFET structure with implanted backgate 有权

    公开(公告)号：US10522663B2

    公开(公告)日：2019-12-31

    申请号：US15999542

    申请日：2018-08-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

    IPC: H01L29/66 ,  H01L29/808 ,  H01L29/10 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/06

    Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

    Transition rate controlled bus driver circuit with reduced load sensitivity
    10.
    发明授权
    Transition rate controlled bus driver circuit with reduced load sensitivity 有权
    转换速率控制总线驱动电路，降低负载灵敏度

    公开(公告)号：US09507409B2

    公开(公告)日：2016-11-29

    申请号：US13923339

    申请日：2013-06-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joel Martin Halbert ,  Vinay Agarwal

    IPC: G06F13/14 ,  G06F1/32 ,  G06F13/38

    CPC classification number: G06F1/3296 ,  G06F13/385

    Abstract: A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).

    Abstract translation: 公开了一种总线驱动器电路（图2）。 电路包括总线（200）和参考端子（Vss）的信号引线。 第一晶体管（MN0）具有第一控制端子并且具有耦合到参考端子的第一电流通路。 第二晶体管（MN1）具有耦合到第一控制端子的第二控制端子，并且具有耦合在信号引线和参考端子之间的第二电流通路。 第三晶体管（MP0）布置成当信号引线处于第一逻辑状态（高）时提供通过第一电流路径的第一电流。 第四晶体管（MP1）被布置成当信号引线处于第二逻辑状态（低）时向第二控制端施加电压。

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