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公开(公告)号：US20180293129A1
公开(公告)日：2018-10-11
申请号：US15482729
申请日：2017-04-08
Applicant: Texas Instruments Incorporated
Inventor： Peter Aberl , Aishwarya Dubey , Rajat Sagar , Eldad Falik
CPC classification number: G11C16/3459 , G06F11/1068 , G11C29/42
Abstract: A device is provided that includes a processor, a flash memory configured to store error correcting code (ECC) blocks for execution in place (XIP) processing by the processor, wherein an ECC block includes a data block and an ECC code for the data block, a flash interface controller coupled to the flash memory, and an error correcting code (ECC) engine coupled between the processor and the flash interface controller, wherein the ECC engine is configured to receive a read command for the flash memory from the processor, to translate a read address to an ECC block address, to read the ECC block at the ECC block address from the flash memory via the flash interface controller, and to verify the ECC code in the read ECC block.
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公开(公告)号：US20240031214A1
公开(公告)日：2024-01-25
申请号：US18479738
申请日：2023-10-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Peter Aberl , Sandeep Rao , Anil Mani
CPC classification number: H04L27/265 , H04B1/40 , H04B1/7102
Abstract: A non-transitory device-readable medium, which may be embodied in a device, such as a radar receiver, stores instructions that, when executed by processing circuitry, are configured to perform operations to identify a region of interference. An analog signal is generated based on received signals reflected from a target object and an interfering object. The analog signal is converted to an initial time-domain data set. Processing circuitry is configured or instructed to perform a transform operation on the initial time-domain data set to generate a frequency-domain data set, based on which a region of interference may be identified. Subsequent operations may be performed to facilitate identification of the region of interest including thresholding, inverse transforming, subtracting, and/or combining. The processing circuitry may be further configured or instructed to generate repaired time-domain data from which corrupted time-domain samples to remove data associated with the interfering object.
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Patent Agency Ranking
公开(公告)号：US20200304611A1
公开(公告)日：2020-09-24
申请号：US16820440
申请日：2020-03-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , Peter Aberl
Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method comprises sampling a first data interface to generate a first data sample. The method further comprises sampling a second data interface to generate a second data sample. The method further comprises combining the first data sample and the second data sample to generate combined data. The method further comprises transmitting the combined data on a sample basis at an Ethernet physical layer of communication.
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公开(公告)号：US11811574B2
公开(公告)日：2023-11-07
申请号：US17722542
申请日：2022-04-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Peter Aberl , Sandeep Rao , Anil Mani
CPC classification number: H04L27/265 , H04B1/40 , H04B1/7102
Abstract: A method is provided. In some examples, the method includes performing, by processing circuitry, a first transform operation on a first time-domain data set to generate a frequency-domain data set. In addition, the method includes determining, by the processing circuitry, that at least one portion of the frequency-domain data set satisfies a first threshold magnitude. The method also includes performing, by the processing circuitry, an inverse transform operation on the at least one portion of the frequency-domain data set to generate a second time-domain data set. The method further includes identifying, by the processing circuitry and based on the second time-domain data set, a region of interference in the first time-domain data set.
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公开(公告)号：US20230231753A1
公开(公告)日：2023-07-20
申请号：US17722542
申请日：2022-04-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Peter Aberl , Sandeep Rao , Anil Mani
CPC classification number: H04L27/265 , H04B1/7102 , H04B1/40
Abstract: A method is provided. In some examples, the method includes performing, by processing circuitry, a first transform operation on a first time-domain data set to generate a frequency-domain data set. In addition, the method includes determining, by the processing circuitry, that at least one portion of the frequency-domain data set satisfies a first threshold magnitude. The method also includes performing, by the processing circuitry, an inverse transform operation on the at least one portion of the frequency-domain data set to generate a second time-domain data set. The method further includes identifying, by the processing circuitry and based on the second time-domain data set, a region of interference in the first time-domain data set.
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公开(公告)号：US11336757B2
公开(公告)日：2022-05-17
申请号：US16820440
申请日：2020-03-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , Peter Aberl
IPC: H04L29/08 , H04L69/323 , G06F5/06
Abstract: A circuit includes a buffer, a first programmable real-time unit (PRU), and a second PRU. The first PRU is coupled to the buffer and configured to couple to an input interface. The first PRU is further configured to receive first data sampled by the input interface and receive second data sampled by the input interface. The first PRU is further configured to multiplex the first data and the second data to generate multiplexed data and transmit the multiplexed data to the buffer. The second PRU is coupled to the buffer and configured to couple to an output interface. The second PRU is further configured to obtain the multiplexed data from the buffer and transmit the multiplexed data via an Ethernet physical layer.
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公开(公告)号：US10388392B2
公开(公告)日：2019-08-20
申请号：US15482729
申请日：2017-04-08
Applicant: Texas Instruments Incorporated
Inventor： Peter Aberl , Aishwarya Dubey , Rajat Sagar , Eldad Falik
Abstract: A device is provided that includes a processor, a flash memory configured to store error correcting code (ECC) blocks for execution in place (XIP) processing by the processor, wherein an ECC block includes a data block and an ECC code for the data block, a flash interface controller coupled to the flash memory, and an error correcting code (ECC) engine coupled between the processor and the flash interface controller, wherein the ECC engine is configured to receive a read command for the flash memory from the processor, to translate a read address to an ECC block address, to read the ECC block at the ECC block address from the flash memory via the flash interface controller, and to verify the ECC code in the read ECC block.
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