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公开(公告)号：US10901692B2
公开(公告)日：2021-01-26
申请号：US16237447
申请日：2018-12-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Indu Prathapan , Puneet Sabbarwal , Pankaj Gupta
Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.
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公开(公告)号：US10747466B2
公开(公告)日：2020-08-18
申请号：US16235897
申请日：2018-12-28
Applicant: Texas Instruments Incorporated
Inventor： Puneet Sabbarwal , Indu Prathapan
Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.
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公开(公告)号：US11537309B2
公开(公告)日：2022-12-27
申请号：US16995542
申请日：2020-08-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Puneet Sabbarwal , Indu Prathapan
Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.
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公开(公告)号：US20210149632A1
公开(公告)日：2021-05-20
申请号：US17156731
申请日：2021-01-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Indu Prathapan , Puneet Sabbarwal , Pankaj Gupta
Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.
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Patent Agency Ranking
公开(公告)号：US12141544B2
公开(公告)日：2024-11-12
申请号：US18335452
申请日：2023-06-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Indu Prathapan , Puneet Sabbarwal , Pankaj Gupta
Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.
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公开(公告)号：US20200210072A1
公开(公告)日：2020-07-02
申请号：US16235897
申请日：2018-12-28
Applicant: Texas Instruments Incorporated
Inventor： Puneet Sabbarwal , Indu Prathapan
Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.
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公开(公告)号：US20230418555A1
公开(公告)日：2023-12-28
申请号：US18335452
申请日：2023-06-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Indu Prathapan , Puneet Sabbarwal , Pankaj Gupta
CPC classification number: G06F7/24 , G06F5/065 , G06F2207/228
Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.
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公开(公告)号：US11714603B2
公开(公告)日：2023-08-01
申请号：US17156731
申请日：2021-01-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Indu Prathapan , Puneet Sabbarwal , Pankaj Gupta
CPC classification number: G06F7/24 , G06F5/065 , G06F2207/228
Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.
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公开(公告)号：US20200379649A1
公开(公告)日：2020-12-03
申请号：US16995542
申请日：2020-08-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Puneet Sabbarwal , Indu Prathapan
Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.
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