公开(公告)号：US20220103179A1

公开(公告)日：2022-03-31

申请号：US17514664

申请日：2021-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Luis FLORES ,  Venkateswar Reddy KOWKUTLA ,  Ramakrishnan VENKATASUBRAMANIAN

IPC: H03L7/08 ,  H03K19/20 ,  G06F1/10 ,  G06F1/08 ,  H03K5/00

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

公开(公告)号：US20210211132A1

公开(公告)日：2021-07-08

申请号：US17078708

申请日：2020-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Luis FLORES ,  Venkateswar Reddy KOWKUTLA ,  Ramakrishnan VENKATASUBRAMANIAN

IPC: H03L7/08 ,  H03K19/20 ,  H03K5/00 ,  G06F1/10 ,  G06F1/08

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.