公开(公告)号：US20230280784A1

公开(公告)日：2023-09-07

申请号：US18317190

申请日：2023-05-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Varun SINGH ,  Rejitha NAIR ,  John Chrysostom APOSTOL ,  Venkateswar Reddy KOWKUTLA ,  Santhanagopal RAGHAVENDRA

IPC: G06F1/12 ,  H03K21/08 ,  G06F1/08 ,  G06F1/10

CPC classification number: G06F1/12 ,  H03K21/08 ,  G06F1/08 ,  G06F1/10 ,  H03K19/20

Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.

公开(公告)号：US20220368444A1

公开(公告)日：2022-11-17

申请号：US17876662

申请日：2022-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US20180227067A1

公开(公告)日：2018-08-09

申请号：US15891227

申请日：2018-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06

CPC classification number: H04J3/0658 ,  H04J3/0641 ,  H04J3/0667 ,  H04J3/0676 ,  H04J3/0679 ,  H04J3/0688 ,  H04J3/0691 ,  H04L7/0083

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US20250030494A1

公开(公告)日：2025-01-23

申请号：US18909428

申请日：2024-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06 ,  H04L7/00

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US20210211132A1

公开(公告)日：2021-07-08

申请号：US17078708

申请日：2020-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Luis FLORES ,  Venkateswar Reddy KOWKUTLA ,  Ramakrishnan VENKATASUBRAMANIAN

IPC: H03L7/08 ,  H03K19/20 ,  H03K5/00 ,  G06F1/10 ,  G06F1/08

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

公开(公告)号：US20210209003A1

公开(公告)日：2021-07-08

申请号：US17138684

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Venkateswar Reddy KOWKUTLA ,  Rejitha NAIR

IPC: G06F11/36 ,  G01R31/317

Abstract: An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.

公开(公告)号：US20230259448A1

公开(公告)日：2023-08-17

申请号：US18305873

申请日：2023-04-24

Applicant: Texas Instruments Incorporated

Inventor： Venkateswar Reddy KOWKUTLA ,  Rejitha NAIR

IPC: G06F11/36 ,  G01R31/317

CPC classification number: G06F11/3648 ,  G06F11/3672 ,  G01R31/31724

Abstract: An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.

公开(公告)号：US20230168709A1

公开(公告)日：2023-06-01

申请号：US17537150

申请日：2021-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Varun SINGH ,  Rejitha NAIR ,  John Chrysostom APOSTOL ,  Venkateswar Reddy KOWKUTLA ,  Raghavendra SANTHANAGOPAL

IPC: G06F1/12 ,  H03K21/08 ,  G06F1/10 ,  G06F1/08

CPC classification number: G06F1/12 ,  H03K21/08 ,  G06F1/10 ,  G06F1/08 ,  H03K19/20

Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.

公开(公告)号：US20220103179A1

公开(公告)日：2022-03-31

申请号：US17514664

申请日：2021-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Luis FLORES ,  Venkateswar Reddy KOWKUTLA ,  Ramakrishnan VENKATASUBRAMANIAN

IPC: H03L7/08 ,  H03K19/20 ,  G06F1/10 ,  G06F1/08 ,  H03K5/00

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

公开(公告)号：US20200059311A1

公开(公告)日：2020-02-20

申请号：US16552353

申请日：2019-08-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.