公开(公告)号：US20250123903A1

公开(公告)日：2025-04-17

申请号：US18999134

申请日：2024-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan VARADARAJAN ,  Varun SINGH ,  Jose Luis FLORES ,  Rejitha NAIR ,  David Matthew THOMPSON

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/32

Abstract: An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.

公开(公告)号：US20220103179A1

公开(公告)日：2022-03-31

申请号：US17514664

申请日：2021-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Luis FLORES ,  Venkateswar Reddy KOWKUTLA ,  Ramakrishnan VENKATASUBRAMANIAN

IPC: H03L7/08 ,  H03K19/20 ,  G06F1/10 ,  G06F1/08 ,  H03K5/00

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

公开(公告)号：US20210208657A1

公开(公告)日：2021-07-08

申请号：US17139249

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Jose Luis FLORES ,  Gary Augustine COOPER ,  Amritpal Singh MUNDRA ,  Anthony LELL ,  Jason Lynn PECK

IPC: G06F1/3203 ,  G06F11/36

Abstract: An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.

公开(公告)号：US20240077925A1

公开(公告)日：2024-03-07

申请号：US18505037

申请日：2023-11-08

Applicant: Texas Instruments Incorporated

Inventor： Jose Luis FLORES ,  Gary Augustine COOPER ,  Amritpal Singh MUNDRA ,  Anthony LELL ,  Jason Lynn PECK

IPC: G06F1/3203 ,  G06F11/36

CPC classification number: G06F1/3203 ,  G06F11/3656

Abstract: Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

公开(公告)号：US20230185633A1

公开(公告)日：2023-06-15

申请号：US17551011

申请日：2021-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan VARADARAJAN ,  Varun SINGH ,  Jose Luis FLORES ,  Rejitha NAIR ,  David Matthew THOMPSON

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/32

CPC classification number: G06F9/5094 ,  G06F9/5016 ,  G06F11/3086 ,  G06F11/321

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

公开(公告)号：US20210211132A1

公开(公告)日：2021-07-08

申请号：US17078708

申请日：2020-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Luis FLORES ,  Venkateswar Reddy KOWKUTLA ,  Ramakrishnan VENKATASUBRAMANIAN

IPC: H03L7/08 ,  H03K19/20 ,  H03K5/00 ,  G06F1/10 ,  G06F1/08

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.