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公开(公告)号:US20200320028A1
公开(公告)日:2020-10-08
申请号:US16909396
申请日:2020-06-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Richard Edwin HUBBARD , Richard Sterling BROUGHTON , Vijayalakshmi DEVARAJAN , Mark Edward WENTROBLE
Abstract: An integrated circuit includes a combined serial data output and interrupt output terminal, a serial communication control circuit; an interrupt generation circuit, and an output circuit. The output circuit includes a serial data input, an interrupt input, and a combined serial data and interrupt output. The serial data input is coupled to a serial data output of the serial communication circuit. The interrupt input is coupled to an interrupt output of the interrupt generation circuit. The combined serial data and interrupt output is coupled to the combined serial data output and interrupt output terminal.
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公开(公告)号:US20200326738A1
公开(公告)日:2020-10-15
申请号:US16914938
申请日:2020-06-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G05F1/46 , H03K17/00 , H03K5/24 , H03K3/3565
Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.
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公开(公告)号:US20220014160A1
公开(公告)日:2022-01-13
申请号:US17487241
申请日:2021-09-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.
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公开(公告)号:US20200350879A1
公开(公告)日:2020-11-05
申请号:US16862089
申请日:2020-04-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.
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公开(公告)号:US20200049754A1
公开(公告)日:2020-02-13
申请号:US16101213
申请日:2018-08-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Richard Edwin HUBBARD , Abhijeeth AAREY PREMANATH , Terry MAYHUGH , Mark Edward WENTROBLE , Wesley Ryan RAY
Abstract: A CAN bus transceiver includes CAN bus fault detection circuitry that can provide detailed information to simplify the task of the service technician when there is a CAN bus fault. Voltage and current measurements of the CAN bus are made and from them a fault type is determined. A time-domain reflectometer monitors the CAN bus signals for transmitted and reflected signals and from them a distance to the fault is determined. Either or both values are provided to a service technician to allow error determination and correction.
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公开(公告)号:US20190354125A1
公开(公告)日:2019-11-21
申请号:US16235631
申请日:2018-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G05F1/46 , H03K3/3565 , H03K5/24 , H03K17/00
Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.
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