公开(公告)号：US20210225711A1

公开(公告)日：2021-07-22

申请号：US17202978

申请日：2021-03-16

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L27/11 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US20190103321A1

公开(公告)日：2019-04-04

申请号：US16206045

申请日：2018-11-30

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/11 ,  H01L21/02 ,  H01L29/20 ,  H01L29/16 ,  H01L27/092 ,  H01L29/10 ,  H01L29/161

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US20160204198A1

公开(公告)日：2016-07-14

申请号：US15079399

申请日：2016-03-24

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/16 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

公开(公告)号：US20150187773A1

公开(公告)日：2015-07-02

申请号：US14573021

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

Abstract translation: 包含n沟道finFET和p沟道finFET的集成电路在硅衬底上具有介电层。 finFET的鳍片具有比硅更高的迁移率的半导体材料。 n沟道finFET的鳍在通过衬底上的电介质层的第一沟槽中的第一硅 - 锗缓冲器上。 p沟道finFET的鳍在通过衬底上的电介质层的第二沟槽中的第二硅 - 锗缓冲器上。 翅片延伸至介电层上方至少10纳米。 散热片通过外延生长在电介质层的沟槽中的硅 - 锗缓冲器上形成，随后CMP平坦化到介电层。 电介质层凹入以暴露翅片。 翅片可以同时或分开地形成。

公开(公告)号：US20160225673A1

公开(公告)日：2016-08-04

申请号：US15079414

申请日：2016-03-24

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L21/8238 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

公开(公告)号：US09053966B2

公开(公告)日：2015-06-09

申请号：US14499834

申请日：2014-09-29

Applicant: Texas Instruments Incorporated

Inventor： Weize W. Xiong ,  Cloves R. Cleavelin ,  Angelo Pinto ,  Rick L. Wise

IPC: H01L29/66 ,  H01L27/088 ,  G11C11/412 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/11 ,  H01L27/092 ,  H01L29/04

CPC classification number: H01L27/0886 ,  G11C11/412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/045 ,  Y10S257/90 ,  Y10S438/973 ,  Y10S438/982

Abstract: An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orienations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

Abstract translation: 公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。 通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体衍射的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。

公开(公告)号：US10978353B2

公开(公告)日：2021-04-13

申请号：US16206045

申请日：2018-11-30

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/161

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US20170033018A1

公开(公告)日：2017-02-02

申请号：US15292373

申请日：2016-10-13

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

Abstract translation: 通过形成用于第一极性finFET的第一极性鳍外延层形成包含n沟道鳍FETFET和p沟道finFET的集成电路，随后形成暴露第二相反极性鳍片外延区域的硬掩模 层用于第二极性finFET。 在由硬掩模暴露的区域中形成第二极性鳍外延层。 翅片掩模限定第一极性鳍片和第二极性鳍片区域，并且随后的鳍片蚀刻形成相应的鳍片。 隔离介质材料层形成在衬底和鳍片之上。 隔离绝缘材料层被平坦化到鳍片。 隔离介电材料层是凹进的，使得翅片在隔离介电材料层之上延伸至少10纳米。 栅极电介质层和栅极形成在鳍片上。

公开(公告)号：US20150187770A1

公开(公告)日：2015-07-02

申请号：US14572949

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

Abstract translation: 通过形成用于第一极性finFET的第一极性鳍外延层形成包含n沟道鳍FETFET和p沟道finFET的集成电路，随后形成暴露第二相反极性鳍片外延区域的硬掩模 层用于第二极性finFET。 在由硬掩模暴露的区域中形成第二极性鳍外延层。 翅片掩模限定第一极性鳍片和第二极性鳍片区域，并且随后的鳍片蚀刻形成相应的鳍片。 隔离介质材料层形成在衬底和鳍片之上。 隔离绝缘材料层被平坦化到鳍片。 隔离介电材料层是凹进的，使得翅片在隔离介电材料层之上延伸至少10纳米。 栅极电介质层和栅极形成在鳍片上。

公开(公告)号：US08872220B2

公开(公告)日：2014-10-28

申请号：US13855520

申请日：2013-04-02

Applicant: Texas Instruments Incorporated

Inventor： Weize W. Xiong ,  Cloves R. Cleavelin ,  Angelo Pinto ,  Rick L. Wise

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/092 ,  H01L27/11 ,  G11C11/412 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  G11C11/412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/045 ,  Y10S257/90 ,  Y10S438/973 ,  Y10S438/982

Abstract: An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

Abstract translation: 公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。 通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体取向的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。