公开(公告)号：US20220367444A1

公开(公告)日：2022-11-17

申请号：US17503877

申请日：2021-10-18

Applicant: Texas Instruments Incorporated

Inventor： Robert Martin Higgins ,  Xiaoju Wu ,  Li Wang ,  Venugopal Balakrishna Menon

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/762

Abstract: A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

公开(公告)号：US20250120169A1

公开(公告)日：2025-04-10

申请号：US18982600

申请日：2024-12-16

Applicant: Texas Instruments Incorporated

Inventor： Robert Martin Higgins ,  Xiaoju Wu ,  Li Wang ,  Venugopal Balakrishna Menon

IPC: H01L27/06 ,  H01L21/762

Abstract: A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

公开(公告)号：US20240312984A1

公开(公告)日：2024-09-19

申请号：US18677190

申请日：2024-05-29

Applicant: Texas Instruments Incorporated

Inventor： Yanbiao Pan ,  Robert Martin Higgins ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

IPC: H01L27/06 ,  H01L21/285

CPC classification number: H01L27/0629 ,  H01L21/28525 ,  H01L21/28556 ,  H01L28/20

Abstract: Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

公开(公告)号：US12199091B2

公开(公告)日：2025-01-14

申请号：US17503877

申请日：2021-10-18

Applicant: Texas Instruments Incorporated

Inventor： Robert Martin Higgins ,  Xiaoju Wu ,  Li Wang ,  Venugopal Balakrishna Menon

IPC: H01L21/00 ,  H01L21/762 ,  H01L27/06 ,  H01L49/02

Abstract: A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

公开(公告)号：US12159846B2

公开(公告)日：2024-12-03

申请号：US16707917

申请日：2019-12-09

Applicant: Texas Instruments Incorporated

Inventor： Richard Allen Faust ,  Robert Martin Higgins ,  Anagha Shashishekhar Kulkarni ,  Jonathan Philip Davis ,  Sudtida Lavangkul ,  Andrew Frank Burnett

IPC: H01L23/00 ,  H01L21/8234

Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

公开(公告)号：US12027515B2

公开(公告)日：2024-07-02

申请号：US17490950

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yanbiao Pan ,  Robert Martin Higgins ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

IPC: H01L27/06 ,  H01L21/285 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/28525 ,  H01L21/28556 ,  H01L28/20

Abstract: Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

公开(公告)号：US20230112644A1

公开(公告)日：2023-04-13

申请号：US17490950

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yanbiao Pan ,  Robert Martin Higgins ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/285

Abstract: Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

公开(公告)号：US20210005560A1

公开(公告)日：2021-01-07

申请号：US16707917

申请日：2019-12-09

Applicant: Texas Instruments Incorporated

Inventor： Richard Allen Faust ,  Robert Martin Higgins ,  Anagha Shashishekhar Kulkarni ,  Jonathan Philip Davis ,  Sudtida Lavangkul ,  Andrew Frank Burnett

IPC: H01L23/00 ,  H01L21/8234

Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.