公开(公告)号：US20210098565A1

公开(公告)日：2021-04-01

申请号：US16584463

申请日：2019-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  David Matthew CURRAN ,  Stephen Arlon MEISNER ,  Bhaskar SRINIVASAN ,  Guruvayurappan S. MATHUR ,  Scott William JESSEN ,  Shih Chang CHANG ,  Russell Duane FIELDS ,  Thomas Terrance LYNCH

IPC: H01L49/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20220069067A1

公开(公告)日：2022-03-03

申请号：US17500096

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  David Matthew CURRAN ,  Stephen Arlon MEISNER ,  Bhaskar SRINIVASAN ,  Guruvayurappan S. MATHUR ,  Scott William JESSEN ,  Shih Chang CHANG ,  Russell Duane FIELDS ,  Thomas Terrance LYNCH

IPC: H01L49/02 ,  H01L21/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20210398910A1

公开(公告)日：2021-12-23

申请号：US17376876

申请日：2021-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adrian SALINAS ,  William Keith McDONALD ,  Scott Alexander JOHANNESMEYER ,  Robert Paul LUCKIN ,  Stephen Arlon MEISNER

IPC: H01L23/544 ,  G03F7/20 ,  H01L21/027

Abstract: An integrated circuit includes a circuit area, and first and second scribe line portions. The first scribe line portion borders a first side of the circuit area, and the second scribe line portion borders a different second side of the circuit area. A plurality of dummy metal structures are located in the first and second scribe line portions, each of the dummy metal structures being located about at a lattice point of a same two-dimensional grid.

公开(公告)号：US20210104468A1

公开(公告)日：2021-04-08

申请号：US16679997

申请日：2019-11-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adrian SALINAS ,  William Keith McDONALD ,  Scott Alexander JOHANNESMEYER ,  Robert Paul LUCKIN ,  Stephen Arlon MEISNER

IPC: H01L23/544 ,  H01L21/027 ,  G03F7/20

Abstract: In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.