公开(公告)号：US20220093507A1

公开(公告)日：2022-03-24

申请号：US17540447

申请日：2021-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  Ye SHAO ,  Guruvayurappan S. MATHUR ,  John K. ARCH ,  Paul STULIK

IPC: H01L23/522 ,  H01G15/00

Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.

公开(公告)号：US20230317774A1

公开(公告)日：2023-10-05

申请号：US17710320

申请日：2022-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei SADOVNIKOV ,  Guruvayurappan S. MATHUR

IPC: H01L29/06 ,  H01L29/73 ,  H01L21/265 ,  H01L29/66 ,  H01L21/761

CPC classification number: H01L29/0619 ,  H01L29/73 ,  H01L21/26513 ,  H01L29/66234 ,  H01L21/761

Abstract: A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

公开(公告)号：US20220069067A1

公开(公告)日：2022-03-03

申请号：US17500096

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  David Matthew CURRAN ,  Stephen Arlon MEISNER ,  Bhaskar SRINIVASAN ,  Guruvayurappan S. MATHUR ,  Scott William JESSEN ,  Shih Chang CHANG ,  Russell Duane FIELDS ,  Thomas Terrance LYNCH

IPC: H01L49/02 ,  H01L21/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20210098565A1

公开(公告)日：2021-04-01

申请号：US16584463

申请日：2019-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  David Matthew CURRAN ,  Stephen Arlon MEISNER ,  Bhaskar SRINIVASAN ,  Guruvayurappan S. MATHUR ,  Scott William JESSEN ,  Shih Chang CHANG ,  Russell Duane FIELDS ,  Thomas Terrance LYNCH

IPC: H01L49/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20210074629A1

公开(公告)日：2021-03-11

申请号：US16561593

申请日：2019-09-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  Ye SHAO ,  Guruvayurappan S. MATHUR ,  John K. ARCH ,  Paul STULIK

IPC: H01L23/522 ,  H01G15/00

Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.

公开(公告)号：US20200328149A1

公开(公告)日：2020-10-15

申请号：US16383176

申请日：2019-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  Bhaskar SRINIVASAN ,  Scott William JESSEN ,  Guruvayurappan S. MATHUR

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.