公开(公告)号：US20220069067A1

公开(公告)日：2022-03-03

申请号：US17500096

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  David Matthew CURRAN ,  Stephen Arlon MEISNER ,  Bhaskar SRINIVASAN ,  Guruvayurappan S. MATHUR ,  Scott William JESSEN ,  Shih Chang CHANG ,  Russell Duane FIELDS ,  Thomas Terrance LYNCH

IPC: H01L49/02 ,  H01L21/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20220005814A1

公开(公告)日：2022-01-06

申请号：US17479542

申请日：2021-09-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Carl Sebastian MORANDI ,  Susan TROLIER-McKINSTRY ,  Kezhakkedath Ramunni UDAYAKUMAR ,  John Anthony RODRIGUEZ ,  Bhaskar SRINIVASAN

IPC: H01L27/11507 ,  H01L49/02

Abstract: In some examples, a system comprises a capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and the second plates and comprising a Bismuth Metal Oxide-Based Lead Titanate thin film. The capacitor further comprises a dielectric layer disposed on a transistor, wherein the capacitor is disposed on the dielectric layer.

公开(公告)号：US20180226418A1

公开(公告)日：2018-08-09

申请号：US15893323

申请日：2018-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Carl Sebastian MORANDI ,  Susan TROLIER-McKINSTRY ,  Kezhakkedath Ramunni UDAYAKUMAR ,  John Anthony RODRIGUEZ ,  Bhaskar SRINIVASAN

IPC: H01L27/11507 ,  H01L49/02

CPC classification number: H01L27/11507 ,  H01L28/55 ,  H01L28/56 ,  H01L28/57

Abstract: In some examples, a system comprises a capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and the second plates and comprising a Bismuth Metal Oxide-Based Lead Titanate thin film. The capacitor further comprises a dielectric layer disposed on a transistor, wherein the capacitor is disposed on the dielectric layer.

公开(公告)号：US20210098565A1

公开(公告)日：2021-04-01

申请号：US16584463

申请日：2019-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  David Matthew CURRAN ,  Stephen Arlon MEISNER ,  Bhaskar SRINIVASAN ,  Guruvayurappan S. MATHUR ,  Scott William JESSEN ,  Shih Chang CHANG ,  Russell Duane FIELDS ,  Thomas Terrance LYNCH

IPC: H01L49/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20200328149A1

公开(公告)日：2020-10-15

申请号：US16383176

申请日：2019-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika FERNANDES ,  Bhaskar SRINIVASAN ,  Scott William JESSEN ,  Guruvayurappan S. MATHUR

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.