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    TRANSCONDUCTANCE SHIFTED DIFFERENTIAL DIFFERENCE AMPLIFIER
    3.
    发明申请
    TRANSCONDUCTANCE SHIFTED DIFFERENTIAL DIFFERENCE AMPLIFIER 审中-公开

    公开(公告)号：US20190158033A1

    公开(公告)日：2019-05-23

    申请号：US15816369

    申请日：2017-11-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Seung Bae Lee ,  Michael Edwin Butenhoff ,  Sudhir Nagaraj

    IPC: H03F1/26 ,  H03F1/34 ,  H03F3/45

    Abstract: Reducing noise for an amplifier-based system circuit that comprises a first differential input pair and a second differential input pair, a first input stage circuit connected to the first differential input pair, wherein the first input stage is configured with a first transconductance value, a second input stage circuit connected to the second differential input pair, wherein the second input stage is configured with a second transconductance value that is less than the first transconductance value, a transimpedance circuit coupled to the first input stage circuit and the second input stage circuit, and a feedback loop circuit coupled to the transimpedance circuit and to the second differential input pair, wherein the feedback loop circuit is not connected to the first differential input pair.

    CURRENT REGULATION IN MOTORS
    6.
    发明申请
    CURRENT REGULATION IN MOTORS 审中-公开

    公开(公告)号：US20170346425A1

    公开(公告)日：2017-11-30

    申请号：US15682008

    申请日：2017-08-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sudhir Nagaraj ,  Anuj Jain

    IPC: H02P7/29 ,  H02P8/22 ,  H02P8/12

    CPC classification number: H02P7/29 ,  H02P8/12 ,  H02P8/22

    Abstract: A motor controller that includes a processing device and a drive circuit. The drive circuit may include a plurality of switches, a motor winding, and a current sensor coupled together in an H-bridge configuration. The processing device is configured to cause a drive current to drive through the motor winding for a minimum amount of time. The processing device is also configured to compare the current through the current sensor to a threshold value at the minimum amount of time. The processing device is also configured to, based on the current being at or above the threshold value at the minimum amount of time, stop the drive current for an off period of time and cause a first decay of the current for a first percentage of the off period of time and a first slow decay for a second percentage of the off period of time.

    DIGITAL-TO-ANALOG SINUSOIDAL DRIVER APPARATUS, SYSTEMS AND METHODS
    7.
    发明申请
    DIGITAL-TO-ANALOG SINUSOIDAL DRIVER APPARATUS, SYSTEMS AND METHODS 有权
    数字到模拟SINUSOIDAL驱动器装置，系统和方法

    公开(公告)号：US20150015176A1

    公开(公告)日：2015-01-15

    申请号：US14135517

    申请日：2013-12-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sudhir Nagaraj ,  Anuj Jain ,  Wenchao Qu

    IPC: H03M1/66 ,  H02P8/22

    CPC classification number: H03M1/661 ,  G06G7/22 ,  H02P8/22

    Abstract: Input codes are sequenced at a lower-resolution linear DAC and the output is converted to a linear current waveform. A first of two interconnected analog current multipliers multiplies the linear current by itself and by the inverse of a first constant current source to create a quadratic current output. A second current multiplier multiplies the quadratic output current by the linear current and by the inverse of a second constant current source to generate a cubic current output. The quadratic and cubic currents are subtracted from the linear current to generate an approximation of the first 180 degrees of a sine wave current. Alternate (pi to 2*pi) positive-going one-half sine waves may be polarity reversed to create a complete positive-going and negative-going sine-shaped electrical current of higher resolution than is available from a sine DAC of resolution equivalent to that of the lower-resolution linear DAC.

    Abstract translation: 输入代码在较低分辨率线性DAC上排序，输出转换为线性电流波形。 两个互连的模拟电流乘法器中的第一个将线性电流本身和第一恒定电流源的反相相乘以产生二次电流输出。 第二个电流倍增器将二次输出电流乘以线性电流和第二恒定电流源的倒数，以产生立方电流输出。 从线性电流中减去二次和三次电流，以产生正弦波电流的前180度的近似。 交替的（pi至2 * pi）正向半正弦波可能会极性反转，以产生比从等效于相同的分辨率的正弦DAC获得的更高分辨率的完整的正向和负向正弦形电流 低分辨率线性DAC的。

    Pulse width modulation technique with time-ratio duty cycle computation
    8.
    发明授权
    Pulse width modulation technique with time-ratio duty cycle computation 有权

    公开(公告)号：US11063577B2

    公开(公告)日：2021-07-13

    申请号：US16896902

    申请日：2020-06-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Paul Vulpoiu ,  Rakesh Raja ,  Sudhir Nagaraj

    IPC: H03K3/017 ,  H03K21/08 ,  H03K5/24 ,  H03K7/08 ,  H03K4/08

    Abstract: An analog signal-to-pulse width modulation (PWM) converter includes a ramp generator generating a ramp signal and a comparator circuit comparing the ramp signal to a first voltage, a second voltage, and to an analog input signal. A duty cycle calculation circuit generates a first control signal to the ramp generator to generate the ramp signal. Based on signals from the comparator circuit, the duty cycle calculation circuit calculates the ratio of the time it takes for the ramp signal to exceed the analog input signal from when the ramp signal exceeds the first voltage to the time it takes for the ramp signal to exceed the second voltage from when the ramp signal exceeds the first voltage. A PWM signal generator generates a PWM output signal based on the ratio calculated by the duty cycle calculation circuit.

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