公开(公告)号：US20180284832A1

公开(公告)日：2018-10-04

申请号：US15473209

申请日：2017-03-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin AGARWAL ,  Rajavelu THINAKARAN ,  Sumit DUBEY

IPC: G05F3/26 ,  H03K5/1252

CPC classification number: G05F3/262 ,  H03K5/1252

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

公开(公告)号：US20250141408A1

公开(公告)日：2025-05-01

申请号：US18498748

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aditya SUNDAR ,  Sumit DUBEY ,  Anand KANNAN

IPC: H03F1/30 ,  H03F3/217

Abstract: In an example, a system includes a loop filter including one or more integrators. The system includes a ramp generator. The system includes a comparator having a first input coupled to an output of the loop filter, a second input coupled to an output of the ramp generator, and having an output. The system includes a mute loop coupled to an input of the loop filter and the output of the comparator. The system includes a power stage having an input coupled to the output of the comparator, and having an output. The system includes a main loop coupled to the output of the power stage and the input of the loop filter. The system includes an integrated error detector having an input coupled to the loop filter, and having an output. The system includes a dual comparator having an input coupled to the output of the integrated error detector.

公开(公告)号：US20210234537A1

公开(公告)日：2021-07-29

申请号：US17232174

申请日：2021-04-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sumit DUBEY ,  Jasjot Singh CHADHA

IPC: H03K5/06 ,  H03K7/08 ,  H03K5/24 ,  H04R3/00

Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.