公开(公告)号：US20190356313A1

公开(公告)日：2019-11-21

申请号：US15980486

申请日：2018-05-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sunil Kashyap Venugopal ,  Karl John Wallinger ,  George Vincent Konnail

IPC: H03K19/003 ,  H03K3/037 ,  G06F1/10

Abstract: In one embodiment, a method includes receiving an output of a first combinational logic at an enable terminal of a first flip-flop. The first combinational logic inputs include a disable first clock signal from a clock switchover circuit and a disable second clock signal from the clock switchover circuit. A set terminal of the first flip-flop receives an output of a logic gate, and the logic gate receives a select signal and a first clock signal. An input terminal of the first flip-flop receives, an output of a second flip-flop. A reset terminal of the first flip-flop receives an output of a second combinational logic. The second combinational logic inputs include a first clock stopped signal, a power-on-reset signal, and the select signal, the first clock stopped signal indicating a stop in the first clock signal. An output terminal of the first flip-flop outputs a modified select signal.

公开(公告)号：US10547311B2

公开(公告)日：2020-01-28

申请号：US15980486

申请日：2018-05-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sunil Kashyap Venugopal ,  Karl John Wallinger ,  George Vincent Konnail

IPC: H03K3/037 ,  H03K19/003 ,  G06F1/10

Abstract: In one embodiment, a method includes receiving an output of a first combinational logic at an enable terminal of a first flip-flop. The first combinational logic inputs include a disable first clock signal from a clock switchover circuit and a disable second clock signal from the clock switchover circuit. A set terminal of the first flip-flop receives an output of a logic gate, and the logic gate receives a select signal and a first clock signal. An input terminal of the first flip-flop receives, an output of a second flip-flop. A reset terminal of the first flip-flop receives an output of a second combinational logic. The second combinational logic inputs include a first clock stopped signal, a power-on-reset signal, and the select signal, the first clock stopped signal indicating a stop in the first clock signal. An output terminal of the first flip-flop outputs a modified select signal.

公开(公告)号：US12019487B2

公开(公告)日：2024-06-25

申请号：US17537997

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Karl John Wallinger ,  Sunil Kashyap Venugopal

IPC: G06F1/26 ,  H02M1/00

CPC classification number: G06F1/26

Abstract: A power management circuit includes a status terminal, an open drain driver, a slot parameter memory, and a slot duration counter. The status terminal is adapted to be coupled to a different power management circuit. The open drain driver is coupled to the status terminal, and is configured to drive the status terminal. The slot parameter memory is configured to store slot parameter values. The slot duration counter is coupled to the slot parameter memory and the open drain driver. The slot duration counter is configured to time a slot duration based on a slot duration value stored in the slot parameter memory, and to activate the open drain driver responsive to expiration of the slot duration.

公开(公告)号：US10578666B2

公开(公告)日：2020-03-03

申请号：US15213140

申请日：2016-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sri Navaneethakrishnan Easwaran ,  Sunil Kashyap Venugopal

IPC: G01R19/04 ,  G01R31/28

Abstract: A circuit comprises a CLVS, a LEA coupled to the CLVS, and a peak detector coupled to the CLVS and the LEA, wherein the peak detector is a switch-based peak detector. A method comprises closing a first switch for a period of time to provide a current to an actuator, opening the first switch after the period, measuring, after the opening, a voltage associated with the actuator, and determining, based on the measuring and using an ADC, whether a diode is present in the actuator and coupled with a correct polarity, is missing, or is present in the actuator and coupled with an incorrect polarity.