公开(公告)号：US20230208369A1

公开(公告)日：2023-06-29

申请号：US18175828

申请日：2023-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suresh Mallala ,  Nitin Agarwal

IPC: H03F3/45 ,  H03F3/30

CPC classification number: H03F3/45192 ,  H03F3/3066 ,  H03F2200/372 ,  H03F2203/45248

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

公开(公告)号：US09477246B2

公开(公告)日：2016-10-25

申请号：US14183739

申请日：2014-02-19

Applicant: Texas Instruments Incorporated

Inventor： Nitin Agarwal ,  Suresh Mallala

IPC: G05F1/575 ,  G05F3/10

CPC classification number: G05F1/575

Abstract: In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The switch is configured to receive an input signal at a first terminal and an error signal at a second terminal and configured to generate an output signal at a third terminal. The first feedback circuit includes a first transistor and a second transistor configured to control the error signal at the second terminal of the switch in response to a difference between the output signal and a reference signal. The second feedback circuit is configured to sense the error signal and generate a tail current at the second node and the fourth node to maintain substantially equal currents in the first transistor and the second transistor, respectively, thereby causing a voltage of the output signal as substantially equal to a voltage of the reference signal.

Abstract translation: 在一个实施例中，公开了一种电压调节器。 电压调节器电路包括开关，第一反馈电路和第二反馈电路。 该开关被配置为在第一终端处接收输入信号，并在第二终端处接收错误信号，并且被配置为在第三终端处产生输出信号。 第一反馈电路包括第一晶体管和第二晶体管，其被配置为响应于输出信号和参考信号之间的差异来控制开关的第二端处的误差信号。 第二反馈电路被配置为感测误差信号并在第二节点和第四节点处产生尾电流，以在第一晶体管和第二晶体管中分别维持基本相等的电流，从而使输出信号的电压基本上 等于参考信号的电压。

公开(公告)号：US08823341B2

公开(公告)日：2014-09-02

申请号：US13658781

申请日：2012-10-23

Applicant: Texas Instruments Incorporated

Inventor： Sudhir Polarouthu ,  Suresh Mallala ,  Ranjit Kumar Dash ,  Sundara Siva Rao Giduturi

IPC: G05F1/00

CPC classification number: H02M3/156 ,  H02M2001/0045 ,  H03F1/0244 ,  H03F3/45183 ,  H03F2203/45674

Abstract: The systems and methods of auto-configurable switching/linear regulation disclosed herein enable a device to operate in both DC-to-DC switching regulation and linear regulation applications. The systems and methods disclosed herein differentiate between switching and linear mode. If the application is for a linear regulator, there will only be a capacitor on the output. If the application is for switching mode regulation, there will be an inductor and a capacitor on the output. Then based on the determination, the mode is selected and the hardware is converted into switching regulator operation or linear regulator operation.

Abstract translation: 本文公开的自动配置开关/线性调节的系统和方法使得器件能够在DC-DC开关调节和线性调节应用中工作。 这里公开的系统和方法区分切换和线性模式。 如果应用用于线性稳压器，输出端将只有一个电容器。 如果应用于开关模式调节，输出端将有一个电感和一个电容。 然后根据确定，选择模式，并将硬件转换为开关稳压器操作或线性稳压器操作。

公开(公告)号：US11595011B2

公开(公告)日：2023-02-28

申请号：US17146523

申请日：2021-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suresh Mallala ,  Nitin Agarwal

IPC: H03F3/45 ,  H03F3/30

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

公开(公告)号：US10924074B2

公开(公告)日：2021-02-16

申请号：US16377462

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suresh Mallala ,  Nitin Agarwal

IPC: H03F3/45 ,  H03F3/30

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

公开(公告)号：US09429971B2

公开(公告)日：2016-08-30

申请号：US14453059

申请日：2014-08-06

Applicant: Texas Instruments Incorporated

Inventor： Suresh Mallala ,  Somshubhra Paul

IPC: H02H3/00 ,  G05F1/569

CPC classification number: G05F1/569 ,  G05F1/573

Abstract: Circuits and methods for providing short-circuit protection in a voltage regulator are disclosed. A voltage regulator includes a pass switch, a voltage error amplifier, a driver circuit, and a short-circuit protection circuit. The pass element is coupled to a power supply and a load, and generates an output voltage in response to a drive signal. The voltage error amplifier generates an error voltage based on a difference of a reference voltage and the output voltage and the driver circuit generates the drive signal in response to the error voltage. The short-circuit protection circuit senses the drive signal and provides a high-resistance path to the driver circuit in a short-circuit event. In a short-circuit event, the high-resistance path clamps current in the driver circuit thereby clamping a voltage difference between the first and third terminals and thereby limiting a load current in the short-circuit event.

Abstract translation: 公开了在电压调节器中提供短路保护的电路和方法。 电压调节器包括通过开关，电压误差放大器，驱动电路和短路保护电路。 传递元件耦合到电源和负载，并且响应于驱动信号而产生输出电压。 电压误差放大器基于参考电压和输出电压的差异产生误差电压，并且驱动器电路响应于误差电压产生驱动信号。 短路保护电路感应驱动信号，并在短路事件中提供驱动电路的高电阻路径。 在短路事件中，高电阻路径夹紧驱动电路中的电流，从而钳位第一和第三端子之间的电压差，从而限制短路事件中的负载电流。

公开(公告)号：US11894817B2

公开(公告)日：2024-02-06

申请号：US18175828

申请日：2023-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suresh Mallala ,  Nitin Agarwal

IPC: H03F3/45 ,  H03F3/30

CPC classification number: H03F3/45192 ,  H03F3/3066 ,  H03F2200/372 ,  H03F2203/45248

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

公开(公告)号：US20200057106A1

公开(公告)日：2020-02-20

申请号：US16538518

申请日：2019-08-12

Applicant: Texas Instruments Incorporated

Inventor： Lakshmanan Balasubramanian ,  Nadeem Husain Tehsildar ,  Rubin Ajit Parekhji ,  Suresh Mallala ,  Nitin Agarwal

IPC: G01R31/3183 ,  G01R31/3167 ,  H03M1/10 ,  G06F17/50

Abstract: In one embodiment, a method of operating a computational system to evaluate a device under test, where the device under test is operable to receive a digital code input and output in response a corresponding output. The method injects a plurality of simulated faults into a pre-silicon model of the device under test. For each injected simulated fault, the method inputs a plurality of digital codes to the model. For each input digital code, the method selectively stores the input digital code if a difference, between a corresponding output for the input digital code and a no-fault output for the input, exceeds a predetermined threshold value.

公开(公告)号：US20160043539A1

公开(公告)日：2016-02-11

申请号：US14453059

申请日：2014-08-06

Applicant: Texas Instruments Incorporated

Inventor： Suresh Mallala ,  Somshubhra Paul

IPC: H02H7/12 ,  H02M3/158

CPC classification number: G05F1/569 ,  G05F1/573

Abstract: Circuits and methods for providing short-circuit protection in a voltage regulator are disclosed. A voltage regulator includes a pass switch, a voltage error amplifier, a driver circuit, and a short-circuit protection circuit. The pass element is coupled to a power supply and a load, and generates an output voltage in response to a drive signal. The voltage error amplifier generates an error voltage based on a difference of a reference voltage and the output voltage and the driver circuit generates the drive signal in response to the error voltage. The short-circuit protection circuit senses the drive signal and provides a high-resistance path to the driver circuit in a short-circuit event. In a short-circuit event, the high-resistance path clamps current in the driver circuit thereby clamping a voltage difference between the first and third terminals and thereby limiting a load current in the short-circuit event.

Abstract translation: 公开了在电压调节器中提供短路保护的电路和方法。 电压调节器包括通过开关，电压误差放大器，驱动电路和短路保护电路。 传递元件耦合到电源和负载，并且响应于驱动信号而产生输出电压。 电压误差放大器基于参考电压和输出电压的差异产生误差电压，并且驱动器电路响应于误差电压产生驱动信号。 短路保护电路感应驱动信号，并在短路事件中提供驱动电路的高电阻路径。 在短路事件中，高电阻路径夹紧驱动电路中的电流，从而钳位第一和第三端子之间的电压差，从而限制短路事件中的负载电流。

公开(公告)号：US20150234404A1

公开(公告)日：2015-08-20

申请号：US14183739

申请日：2014-02-19

Applicant: Texas Instruments Incorporated

Inventor： Nitin Agarwal ,  Suresh Mallala

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The switch is configured to receive an input signal at a first terminal and an error signal at a second terminal and configured to generate an output signal at a third terminal. The first feedback circuit includes a first transistor and a second transistor configured to control the error signal at the second terminal of the switch in response to a difference between the output signal and a reference signal. The second feedback circuit is configured to sense the error signal and generate a tail current at the second node and the fourth node to maintain substantially equal currents in the first transistor and the second transistor, respectively, thereby causing a voltage of the output signal as substantially equal to a voltage of the reference signal.

Abstract translation: 在一个实施例中，公开了一种电压调节器。 电压调节器电路包括开关，第一反馈电路和第二反馈电路。 该开关被配置为在第一终端处接收输入信号，并在第二终端处接收错误信号，并且被配置为在第三终端处产生输出信号。 第一反馈电路包括第一晶体管和第二晶体管，其被配置为响应于输出信号和参考信号之间的差异来控制开关的第二端处的误差信号。 第二反馈电路被配置为感测误差信号并在第二节点和第四节点处产生尾电流，以在第一晶体管和第二晶体管中分别维持基本上相等的电流，从而使输出信号的电压基本上 等于参考信号的电压。