MONOLITHIC REFERENCE ARCHITECTURE WITH BURST MODE SUPPORT
    1.
    发明申请
    MONOLITHIC REFERENCE ARCHITECTURE WITH BURST MODE SUPPORT 审中-公开
    具有BURST模式支持的单片参考架构

    公开(公告)号:US20170068265A1

    公开(公告)日:2017-03-09

    申请号:US15259368

    申请日:2016-09-08

    CPC classification number: G05F1/575

    Abstract: A reference circuit may include a bandgap reference stage, a filter stage, and a buffer stage. The reference stage may be configured to generate a reference voltage or current. The filter stage may be coupled to the reference stage and may be configured to receive the reference voltage or current, filter noise from the reference voltage or current, receive a buffer output voltage or current, and filter noise from the buffer output voltage or current. The buffer stage may be coupled to the filter stage and may be configured to isolate the reference stage and the filter stage from a loading effect of a load circuit and generate a reference signal based on the reference voltage or current to drive the load circuit.

    Abstract translation: 参考电路可以包括带隙基准级,滤波级和缓冲级。 参考级可以被配置为产生参考电压或电流。 滤波器级可以耦合到参考级,并且可以被配置为从参考电压或电流接收参考电压或电流,滤波器噪声,接收缓冲器输出电压或电流,以及从缓冲器输出电压或电流滤除噪声。 缓冲级可以耦合到滤波器级,并且可以被配置为将参考级和滤波级与负载电路的负载效应隔离,并且基于参考电压或电流产生参考信号以驱动负载电路。

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