公开(公告)号：US20250103789A1

公开(公告)日：2025-03-27

申请号：US18974920

申请日：2024-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar SURENDRAN ,  Venkatraman RAMAKRISHNAN

IPC: G06F30/398 ,  G06F30/3312

Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.

公开(公告)号：US20210255682A1

公开(公告)日：2021-08-19

申请号：US17156910

申请日：2021-01-25

Applicant: Texas Instruments Incorporated

Inventor： Lakshmanan BALASUBRAMANIAN ,  Aswani Kumar GOLLA ,  Venkatraman RAMAKRISHNAN ,  Sushmitha Tudiyadka GIRIJASHANKAR

IPC: G06F1/26

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.

公开(公告)号：US20240078369A1

公开(公告)日：2024-03-07

申请号：US17899252

申请日：2022-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan BALASUBRAMANIAN ,  Venkatraman RAMAKRISHNAN

IPC: G06F30/367 ,  H03K19/0948 ,  H03K19/20

CPC classification number: G06F30/367 ,  H03K19/0948 ,  H03K19/20 ,  G06F2119/06

Abstract: A “weak” undriven state is defined as a signal state, distinguished from conventional unknown and high impedance states, and methods of representing this “weak” undriven state in circuit modelling and power aware digital/mixed-signal simulations for comprehensive and complete RTL-level design verification. The conventional unknown state refers to a circuit element that is powered but has an unknown value, a circuit element that is not powered, or a circuit element having an undriven, floating signal. The unknown state is modified, and the “weak” undriven state refers to a circuit element that is not powered and has an unknown value. The “weak” undriven state can have an electrically high impedance to known supply or ground when no other circuit element is active. The “weak” undriven state distinction is particularly useful to model and verify circuit designs known to be resilient to “weak” undriven states, using event driven logic circuit simulators.

公开(公告)号：US20230195984A1

公开(公告)日：2023-06-22

申请号：US17559442

申请日：2021-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ajoy MANDAL ,  Venkatraman RAMAKRISHNAN ,  Steven BARTLING

IPC: G06F30/3312

CPC classification number: G06F30/3312 ,  G06F2119/12

Abstract: A method for timing analysis includes receiving a physical design of an electric circuit, selecting a timing path within the electric circuit, and determining that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor. The method further includes running a set of process corners with the first type of transistor at a given corner and the second type of transistor at a condition other than the given corner. The first type of transistor has a delay that is based on process correlation with the second type of transistor. The method also includes determining whether a timing requirement is met or not met for the selected timing path, and then reporting whether the timing requirement is met or not met.

公开(公告)号：US20230110701A1

公开(公告)日：2023-04-13

申请号：US17560646

申请日：2021-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar SURENDRAN ,  Venkatraman RAMAKRISHNAN

IPC: G06F30/3323 ,  G06F30/327

Abstract: A technique for domain crossing verification including receiving a first data object representation of an electrical circuit, performing a domain crossing check on the first data object representation to identify a domain crossing issue, receiving an indication of an assumption for the identified domain crossing issue, converting the first data object representation of the electrical circuit to a second data object representation of the electrical circuit, wherein the second data object representation is synthesized based on the first data object representation, determining one or more verification checks based on the second data object representation and the assumption for the identified domain crossing issue, and performing the one or more verification checks on the second data object representation of the electrical circuit.

公开(公告)号：US20230244841A1

公开(公告)日：2023-08-03

申请号：US17589317

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar SURENDRAN ,  Venkatraman RAMAKRISHNAN

IPC: G06F30/3312

CPC classification number: G06F30/3312 ,  G06F2115/08

Abstract: A method includes obtaining, by a computer processor according to computer instructions, data models of intellectual property (IP) cores for hierarchical clock domain crossing (CDC) and reset domain crossing (RDC) verification, where the IP cores include reusable units of logic for a system on a chip (SoC), and performing, by the computer processor based on the data models of the IP cores, the hierarchical CDC and RDC verification for the SoC according to integration of the IP cores in the SoC, where the hierarchical CDC and RDC verification includes consistency verification of functional assumptions with structural analysis of the IP cores individually and in a context of use in the SoC.

公开(公告)号：US20230205969A1

公开(公告)日：2023-06-29

申请号：US17562728

申请日：2021-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar SURENDRAN ,  Venkatraman RAMAKRISHNAN

IPC: G06F30/398 ,  G06F30/3312

CPC classification number: G06F30/398 ,  G06F30/3312

Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.