公开(公告)号：US20250103789A1

公开(公告)日：2025-03-27

申请号：US18974920

申请日：2024-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar SURENDRAN ,  Venkatraman RAMAKRISHNAN

IPC: G06F30/398 ,  G06F30/3312

Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.

公开(公告)号：US20230110701A1

公开(公告)日：2023-04-13

申请号：US17560646

申请日：2021-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar SURENDRAN ,  Venkatraman RAMAKRISHNAN

IPC: G06F30/3323 ,  G06F30/327

Abstract: A technique for domain crossing verification including receiving a first data object representation of an electrical circuit, performing a domain crossing check on the first data object representation to identify a domain crossing issue, receiving an indication of an assumption for the identified domain crossing issue, converting the first data object representation of the electrical circuit to a second data object representation of the electrical circuit, wherein the second data object representation is synthesized based on the first data object representation, determining one or more verification checks based on the second data object representation and the assumption for the identified domain crossing issue, and performing the one or more verification checks on the second data object representation of the electrical circuit.

公开(公告)号：US20230102099A1

公开(公告)日：2023-03-30

申请号：US17563398

申请日：2021-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan RAJU ,  Sudhakar SURENDRAN ,  Anand Kumar G

IPC: G06F11/14 ,  G06F11/07 ,  G06F13/40 ,  G06F13/16 ,  G06F21/60

Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

公开(公告)号：US20230244841A1

公开(公告)日：2023-08-03

申请号：US17589317

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar SURENDRAN ,  Venkatraman RAMAKRISHNAN

IPC: G06F30/3312

CPC classification number: G06F30/3312 ,  G06F2115/08

Abstract: A method includes obtaining, by a computer processor according to computer instructions, data models of intellectual property (IP) cores for hierarchical clock domain crossing (CDC) and reset domain crossing (RDC) verification, where the IP cores include reusable units of logic for a system on a chip (SoC), and performing, by the computer processor based on the data models of the IP cores, the hierarchical CDC and RDC verification for the SoC according to integration of the IP cores in the SoC, where the hierarchical CDC and RDC verification includes consistency verification of functional assumptions with structural analysis of the IP cores individually and in a context of use in the SoC.

公开(公告)号：US20230205969A1

公开(公告)日：2023-06-29

申请号：US17562728

申请日：2021-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar SURENDRAN ,  Venkatraman RAMAKRISHNAN

IPC: G06F30/398 ,  G06F30/3312

CPC classification number: G06F30/398 ,  G06F30/3312

Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.