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公开(公告)号:US20220209756A1
公开(公告)日:2022-06-30
申请号:US17135395
申请日:2020-12-28
发明人: Vibha GOENKA
IPC分类号: H03K5/1252 , H03K3/017 , H03K3/037 , H03K5/24 , H03K19/20
摘要: A circuit includes a first delay filter, a first comparator, an inverter, a second delay filter, a second comparator, an OR gate, and a latch. A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output, and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a deglitched signal.
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公开(公告)号:US20210203346A1
公开(公告)日:2021-07-01
申请号:US16732213
申请日:2019-12-31
发明人: Vibha GOENKA , Preetam Charan Anand TADEPARTHY , Vikram GAKHAR , Muthusubramanian VENKATESWARAN , Siddaram MATHAPATHI
摘要: In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.
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