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公开(公告)号:US20240113623A1
公开(公告)日:2024-04-04
申请号:US18539346
申请日:2023-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Bikash Kumar PRADHAN , Preetam Charan Anand TADEPARTHY , Muthusubramanian VENKATESWARAN , Venkatesh WADEYAR , Siddaram MATHAPATHI
CPC classification number: H02M3/158 , H02M1/00 , H02M1/0045
Abstract: A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.
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公开(公告)号:US20230170796A1
公开(公告)日:2023-06-01
申请号:US17537595
申请日:2021-11-30
Applicant: Texas Instruments Incorporated
Inventor: Muthusubramanian VENKATESWARAN , Rohit NARULA , Preetam Charan Anand TADEPARTHY , Matthew John Ascher SCHURMANN , Rajesh VENUGOPAL
Abstract: A multiphase controller includes an integrator enable terminal, a pulse width modulator, an error integrator, an open drain driver, and an integrator enable circuit. The integrator enable terminal is adapted to be coupled to the integrator enable terminal of a different instance of the multiphase controller. The pulse width modulator is configured to modulate a power stage. The error integrator is configured to control the pulse width modulator. The open drain driver is coupled to the integrator enable circuit. The integrator enable circuit is coupled to the pulse width modulator, the error integrator, the open drain driver, and the integrator enable terminal. The integrator enable circuit is configured to activate the open drain driver responsive to generation of a power stage control pulse by the pulse width modulator, and activate the error integrator responsive to a logic low signal at the integrator enable terminal.
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公开(公告)号:US20220294344A1
公开(公告)日:2022-09-15
申请号:US17200564
申请日:2021-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Bikash Kumar PRADHAN , Preetam Charan Anand TADEPARTHY , Muthusubramanian VENKATESWARAN , Venkatesh WADEYAR , Siddaram MATHAPATHI
Abstract: A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.
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公开(公告)号:US20240214002A1
公开(公告)日:2024-06-27
申请号:US18086204
申请日:2022-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Vishal SHAW , Preetam Charan Anand TADEPARTHY , Mayank JAIN
CPC classification number: H03M1/822 , H03M1/0626 , H03M1/1205
Abstract: In an example, an apparatus includes a first decoder circuit having a first voltage identification (VID) analog input and a first digital output. The apparatus also includes a precharge circuit having a digital input and a first analog output, the digital input coupled to the first digital output. The apparatus also includes a second decoder circuit having a second VID analog input, a precharge analog input and a second digital output, the precharge analog input coupled to the first digital output. The apparatus also includes a multiplexer having a multiplexer output and first and second multiplexer inputs, the first multiplexer input coupled to the first digital output, and the second multiplexer input coupled to the second digital output.
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公开(公告)号:US20220393464A1
公开(公告)日:2022-12-08
申请号:US17339576
申请日:2021-06-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Rajesh VENUGOPAL , Matthew John Ascher SCHURMANN , Preetam Charan Anand TADEPARTHY , Rengang CHEN
IPC: H02J1/10 , G06F1/3203 , H02M3/158
Abstract: A system includes a first power stage circuit having a first PWM input, a first voltage input and a first power output. The first power stage circuit is configured to provide a first current at the first power output responsive to a PWM signal at the first PWM input, and configured to receive a voltage at the first voltage input. The system includes a second power stage circuit having a second PWM input, a second voltage input and a second power output. The second voltage input is coupled to the first voltage input, and the second power stage circuit is configured to provide a second current at the second power output responsive to the PWM signal at the second PWM input. The second power stage circuit is configured to receive the voltage at the second voltage input, the voltage representing an average of the first current and the second current.
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公开(公告)号:US20220149792A1
公开(公告)日:2022-05-12
申请号:US17514087
申请日:2021-10-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An amplifier includes a first stage and a second stage. The first stage is configured to amplify a received signal. The second stage is coupled to the first stage. The second stage includes a source follower and a compensation network. The source follower includes an input and an output. The compensation network is coupled to the input of the source follower and the output of the source follower. The compensation network is configured to modify a magnitude and phase response of the first stage based on a load capacitance coupled to the output of the source follower.
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公开(公告)号:US20210203346A1
公开(公告)日:2021-07-01
申请号:US16732213
申请日:2019-12-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Vibha GOENKA , Preetam Charan Anand TADEPARTHY , Vikram GAKHAR , Muthusubramanian VENKATESWARAN , Siddaram MATHAPATHI
Abstract: In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.
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公开(公告)号:US20230378869A1
公开(公告)日:2023-11-23
申请号:US18229755
申请日:2023-08-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Naman BAFNA , Preetam Charan Anand TADEPARTHY , Ammineni BALAJI , Sreelakshmi SURESH , Mayank JAIN
CPC classification number: H02M3/157 , H02M1/0845 , H02M1/0009
Abstract: In an example, a method includes storing a pending PWM pulse for a switching voltage regulator. The method also includes determining a switching voltage regulator is operating in a current limit mode, where an inductor current is above a current limit threshold. The method includes providing a predetermined number of PWM pulses in the current limit mode. The method also includes, responsive to providing the predetermined number of PWM pulses, ceasing storage of pending PWM pulses for the switching voltage regulator.
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公开(公告)号:US20220393588A1
公开(公告)日:2022-12-08
申请号:US17490671
申请日:2021-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Naman BAFNA , Preetam Charan Anand TADEPARTHY , Ammineni BALAJI , Sreelakshmi SURESH , Mayank JAIN
Abstract: In an example, a method includes storing a pending PWM pulse for a switching voltage regulator. The method also includes determining a switching voltage regulator is operating in a current limit mode, where an inductor current is above a current limit threshold. The method includes providing a predetermined number of PWM pulses in the current limit mode. The method also includes, responsive to providing the predetermined number of PWM pulses, ceasing storage of pending PWM pulses for the switching voltage regulator.
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公开(公告)号:US20220271664A1
公开(公告)日:2022-08-25
申请号:US17678220
申请日:2022-02-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Vishnuvardhan Reddy JALADANKI , Preetam Charan Anand TADEPARTHY , Scott RAGONA , Rengang CHEN , Evan Michael REUTZEL , Bhaskar RAMACHANDRAN
Abstract: A device includes a current mirror, a switch, first and second current paths, first and second buffers, a variable resistor, a temperature-sensing circuit, and a controller. The first current path is coupled between the current mirror's input and the switch. The switch switches between ground and a transistor based on a control signal. The second current path is coupled between a first current mirror output and ground. The first buffer is coupled to a second current mirror output. The second buffer is coupled to the variable resistor, which is coupled to the first buffer. The temperature-sensing circuit provides a device temperature to the controller, which is coupled to a first buffer output and determines a first adjustment to the first and second current paths and a second adjustment to the variable resistor based on the device temperature.
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