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1.发明授权公开(公告)号：US09507409B2
公开(公告)日：2016-11-29
申请号：US13923339
申请日：2013-06-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Joel Martin Halbert , Vinay Agarwal
CPC classification number: G06F1/3296 , G06F13/385
Abstract: A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).
Abstract translation: 公开了一种总线驱动器电路（图2）。 电路包括总线（200）和参考端子（Vss）的信号引线。 第一晶体管（MN0）具有第一控制端子并且具有耦合到参考端子的第一电流通路。 第二晶体管（MN1）具有耦合到第一控制端子的第二控制端子，并且具有耦合在信号引线和参考端子之间的第二电流通路。 第三晶体管（MP0）布置成当信号引线处于第一逻辑状态（高）时提供通过第一电流路径的第一电流。 第四晶体管（MP1）被布置成当信号引线处于第二逻辑状态（低）时向第二控制端施加电压。
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2.发明申请TRANSITION RATE CONTROLLED BUS DRIVER CIRCUIT WITH REDUCED LOAD SENSITIVITY 有权具有降低负载灵敏度的转换速率控制总线驱动电路公开(公告)号：US20140380065A1
公开(公告)日：2014-12-25
申请号：US13923339
申请日：2013-06-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Joel Martin Halbert , Vinay Agarwal
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F13/385
Abstract: A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).
Abstract translation: 公开了一种总线驱动器电路（图2）。 电路包括总线（200）和参考端子（Vss）的信号引线。 第一晶体管（MN0）具有第一控制端子并且具有耦合到参考端子的第一电流通路。 第二晶体管（MN1）具有耦合到第一控制端子的第二控制端子，并且具有耦合在信号引线和参考端子之间的第二电流通路。 第三晶体管（MP0）布置成当信号引线处于第一逻辑状态（高）时提供通过第一电流路径的第一电流。 第四晶体管（MP1）被布置成当信号引线处于第二逻辑状态（低）时向第二控制端施加电压。
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