公开(公告)号：US10135430B2

公开(公告)日：2018-11-20

申请号：US15272035

申请日：2016-09-21

Applicant: Texas Instruments Incorporated

Inventor： Suheng Chen ,  Daniel Andrew Mavencamp ,  Wang Li

IPC: H03B1/00 ,  H03K3/00 ,  H03K5/19 ,  H03K17/687

Abstract: A system that can include a detector that can monitor a voltage at an input of a transistor device over a period of time and provide a signal having a value representative of a capacitance between the input and an output of the transistor device. The system can further include a driver that can have a programmable drive strength and be coupled to input of the transistor device to drive the transistor device at the input thereof. The system can further include a controller that can configure the driver based on the signal to drive the transistor device with a corresponding drive strength.

公开(公告)号：US20170207780A1

公开(公告)日：2017-07-20

申请号：US15272035

申请日：2016-09-21

Applicant: Texas Instruments Incorporated

Inventor： Suheng Chen ,  Daniel Andrew Mavencamp ,  Wang Li

IPC: H03K5/19 ,  H03K17/687

CPC classification number: H03K5/19 ,  H03K17/04123 ,  H03K17/163 ,  H03K17/687

Abstract: A system that can include a detector that can monitor a voltage at an input of a transistor device over a period of time and provide a signal having a value representative of a capacitance between the input and an output of the transistor device. The system can further include a driver that can have a programmable drive strength and be coupled to input of the transistor device to drive the transistor device at the input thereof. The system can further include a controller that can configure the driver based on the signal to drive the transistor device with a corresponding drive strength.

公开(公告)号：US10763853B2

公开(公告)日：2020-09-01

申请号：US16137326

申请日：2018-09-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wang Li ,  Qiong M. Li ,  Yipeng Su

IPC: H03K17/687 ,  H02J7/00 ,  H03K17/66 ,  H02J1/10 ,  H02J7/34

Abstract: In an example, a circuit comprising a first inductor coupled between a first node and a second node, a first PMOS having a source terminal coupled to the second node and a drain terminal coupled to a third node, a second PMOS having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the second node, a third PMOS having a source terminal coupled to a fourth node and a drain terminal coupled to the third node, a fourth PMOS having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fourth node, a NMOS having a source terminal coupled to the third node and a drain terminal coupled to a fifth node, a second inductor coupled between the fourth node and the fifth node, and a controller.