NODE SYNCHRONIZATION FOR NETWORKS
    1.
    发明公开

    公开(公告)号:US20240147391A1

    公开(公告)日:2024-05-02

    申请号:US18406881

    申请日:2024-01-08

    CPC classification number: H04W56/001 H04W76/25

    Abstract: A network includes an intermediate node to communicate with a child node via a wireless network protocol. An intermediate node synchronizer in the intermediate node facilitates time synchronization with its parent node and with the child node. A child node synchronizer in the child node to facilitates time synchronization with the intermediate node. The intermediate node synchronizer exchanges synchronization data with the child node synchronizer to enable the child node to be time synchronized to the intermediate node before the intermediate node is synchronized to its parent node if the intermediate node has not synchronized to its parent node within a predetermined guard time period established for the child node.

    NODE CONFIGURATION AND SELF-HEALING FOR AD HOC NETWORKS

    公开(公告)号:US20170353910A1

    公开(公告)日:2017-12-07

    申请号:US15591867

    申请日:2017-05-10

    Abstract: A network includes at least one node to communicate with at least one other node via a wireless network protocol. The node includes a network configuration module to periodically switch a current node function of the node between an intermediate node function and a leaf node function. The switch of the current node function enables automatic reconfiguration of the wireless network based on detected communications between the at least one node and at least one intermediate node or at least one leaf node via the wireless network protocol.

    NODE SYNCHRONIZATION FOR NETWORKS

    公开(公告)号:US20210314887A1

    公开(公告)日:2021-10-07

    申请号:US17353872

    申请日:2021-06-22

    Abstract: A network includes an intermediate node to communicate with a child node via a wireless network protocol. An intermediate node synchronizer in the intermediate node facilitates time synchronization with its parent node and with the child node. A child node synchronizer in the child node to facilitates time synchronization with the intermediate node. The intermediate node synchronizer exchanges synchronization data with the child node synchronizer to enable the child node to be time synchronized to the intermediate node before the intermediate node is synchronized to its parent node if the intermediate node has not synchronized to its parent node within a predetermined guard time period established for the child node.

    NODE SYNCHRONIZATION FOR NETWORKS
    8.
    发明公开

    公开(公告)号:US20230156641A1

    公开(公告)日:2023-05-18

    申请号:US18157921

    申请日:2023-01-23

    CPC classification number: H04W56/001 H04W76/25

    Abstract: A network includes an intermediate node to communicate with a child node via a wireless network protocol. An intermediate node synchronizer in the intermediate node facilitates time synchronization with its parent node and with the child node. A child node synchronizer in the child node to facilitates time synchronization with the intermediate node. The intermediate node synchronizer exchanges synchronization data with the child node synchronizer to enable the child node to be time synchronized to the intermediate node before the intermediate node is synchronized to its parent node if the intermediate node has not synchronized to its parent node within a predetermined guard time period established for the child node.

    DATA FRAME FOR PLC HAVING DESTINATION ADDRESS IN THE PHY HEADER
    9.
    发明申请
    DATA FRAME FOR PLC HAVING DESTINATION ADDRESS IN THE PHY HEADER 审中-公开
    数据帧用于PLC中的目标地址在PHY头

    公开(公告)号:US20150085881A1

    公开(公告)日:2015-03-26

    申请号:US14556373

    申请日:2014-12-01

    CPC classification number: H04L69/22 H04B3/54 H04B3/542 H04B2203/5408

    Abstract: A physical layer (PHY) data frame for use in conjunction with processor in a node, processor coupled to a program memory for storing a sequence of operating instructions. The frame has a preamble, PHY header, a MAC header and a MAC payload. The PHY header includes a destination address field having a destination address therein. The destination address is used by the processor to determine match with the node address.

    Abstract translation: 与节点中的处理器结合使用的物理层(PHY)数据帧,耦合到程序存储器的处理器,用于存储操作指令序列。 帧具有前同步码,PHY报头,MAC报头和MAC有效载荷。 PHY标头包括其中具有目的地地址的目的地地址字段。 处理器使用目的地地址来确定与节点地址的匹配。

    MONOPOLE ANTENNA DESIGN FOR IMPROVED RF ANTENNA EFFICIENCY

    公开(公告)号:US20230050792A1

    公开(公告)日:2023-02-16

    申请号:US17888447

    申请日:2022-08-15

    Abstract: An electronic device includes a printed circuit board (PCB) with electronics configured to generate and receive data by a radio-frequency carrier signal via a signal terminal. A monopole antenna having first and second ends is connected to a signal terminal of the PCB at the first end. A first section of the antenna extends away from the signal terminal by a first length in a first direction. A second section of the antenna extends away from the first section by a second greater length in a second direction different from the first direction. The first section is spaced apart from the PCB by a third section of the antenna, and the second end of the antenna is spaced apart from the PCB by a dielectric spacer. The length of the antenna may be ¼ of a carrier frequency provided by the signal terminal.

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