公开(公告)号：US12192024B2

公开(公告)日：2025-01-07

申请号：US17103711

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Bassam N. Coury ,  Sujoy Sen ,  Thomas E. Willis ,  Durgesh Srivastava

IPC: H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

Abstract: Examples described herein includes a network interface controller comprising a memory interface and a network interface, the network interface controller configurable to provide access to local memory and remote memory to a requester, wherein the network interface controller is configured with an amount of memory of different memory access speeds for allocation to one or more requesters. In some examples, the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester. In some examples, the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester. In some examples, the network interface controller is to regulate quality of service of memory access requests from requesters.

公开(公告)号：US12192023B2

公开(公告)日：2025-01-07

申请号：US17103602

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Durgesh Srivastava ,  Thomas E. Willis ,  Bassam N. Coury ,  Marcelo Cintra

IPC: H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

Abstract: Examples described herein and includes at least one processor and a direct memory access (DMA) device. In some examples, the DMA device is to: access a command from a memory region allocated to receive commands for execution by the DMA device, wherein the command is to access content from a local memory device or remote memory node. In some examples, the DMA device is to: determine if the content is stored in a local memory device or a remote memory node based on a configuration that indicates whether a source address refers to a memory address associated with the local memory device or the remote memory node and whether a destination address refers to a memory address associated with the local memory device or the remote memory node. In some examples, the DMA device is to: copy the content from a local memory device or copy the content to the local memory device using a memory interface.

公开(公告)号：US12132581B2

公开(公告)日：2024-10-29

申请号：US17103802

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Durgesh Srivastava ,  Thomas E. Willis ,  Bassam N. Coury ,  Marcelo Cintra

IPC: H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

CPC classification number: H04L12/1868 ,  G06F12/0238 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/1689 ,  G06F13/28 ,  G06F13/4059 ,  H04L12/5601 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  G06F2213/28 ,  H04L2012/562

Abstract: Examples described herein includes an apparatus comprising: a network interface configured to: receive a request to copy data from a local memory to a remote memory; based on a configuration that the network interface is to manage a cache store the data into the cache and record that the data is stored in the cache. In some examples, store the data in the cache comprises store most recently evicted data from the local memory into the cache. In some examples, the network interface is to store data evicted from the local memory that is not stored into the cache into one or more remote memories.

公开(公告)号：US20240244012A1

公开(公告)日：2024-07-18

申请号：US18623693

申请日：2024-04-01

Applicant: Cisco Technology, Inc.

Inventor： Javed ASGHAR ,  Sridhar VALLEPALLI ,  Umamaheswararao KARYAMPUDI ,  Srinivas KOTAMRAJU

IPC: H04L49/104 ,  H04L9/40 ,  H04L12/46 ,  H04L41/0893 ,  H04L45/02 ,  H04L45/16 ,  H04L45/24 ,  H04L45/74 ,  H04L49/15 ,  H04L49/201 ,  H04L61/106 ,  H04L69/22

CPC classification number: H04L49/104 ,  H04L12/462 ,  H04L12/4633 ,  H04L41/0893 ,  H04L45/04 ,  H04L45/16 ,  H04L45/24 ,  H04L45/74 ,  H04L49/1553 ,  H04L49/203 ,  H04L61/106 ,  H04L63/20 ,  H04L69/22

Abstract: An endpoint group (EPG) can be stretched between the sites so that endpoints at different sites can be assigned to the same stretched EPG. Because the sites can use different bridge domains when establishing the stretched EPGs, the first time a site transmits a packet to an endpoint in a different site, the site learns or discovers a path to the destination endpoint. The site can use BGP to identify the site with the host and use a multicast tunnel to reach the site. A unicast tunnel can be used to transmit future packets to the destination endpoint. Additionally, a stretched EPG can be segmented to form a micro-stretched EPG. Filtering criteria can be used to identify a subset of the endpoints in the stretched EPG that are then assigned to the micro-stretched EPG, which can have different policies than the stretched EPG.

公开(公告)号：US11968132B2

公开(公告)日：2024-04-23

申请号：US16104495

申请日：2018-08-17

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Bjørn Dag Johnsen ,  Line Holen ,  Dag Georg Moxnes

IPC: H04L49/356 ,  H04L45/02 ,  H04L45/16 ,  H04L45/48 ,  H04L49/201 ,  H04L67/025 ,  H04L67/1097 ,  H04L67/51 ,  H04L67/563 ,  H04L67/564 ,  H04L67/568 ,  H04L69/24

CPC classification number: H04L49/358 ,  H04L45/02 ,  H04L45/16 ,  H04L45/48 ,  H04L49/201 ,  H04L67/025 ,  H04L67/1097 ,  H04L67/51 ,  H04L67/563 ,  H04L67/564 ,  H04L67/568 ,  H04L69/24

Abstract: Systems and methods for using queue pair 1 (QP1) for receiving multicast based announcements in multiple partitions in a high performance computing. In accordance with an embodiment, by extending the scope of QP1 to also include receiving and sending multicast packets in any partition defined for the port, it is possible to implement generic MC based announcement and discovery without requiring the complexity of unique QPs for individual partitions, nor any update of QP configuration as a consequence of change of partition membership.

公开(公告)号：US11652733B2

公开(公告)日：2023-05-16

申请号：US17105042

申请日：2020-11-25

Applicant: Arista Networks, Inc.

Inventor： Charanjith Reddy Kunduru ,  Sudip Regmi

IPC: H04L45/16 ,  H04L45/00 ,  H04L45/021 ,  H04L41/08 ,  H04L49/201

CPC classification number: H04L45/16 ,  H04L41/08 ,  H04L45/021 ,  H04L45/34 ,  H04L49/201

Abstract: Techniques for operating a networking switch in two broadcast networks are provided. In some embodiments, the switch may instantiate a first controller client and a second controller client in a control plane of the switch; register the first controller client with a first broadcast controller associated with a first broadcast network; and register the second controller client with a second broadcast controller associated with a second broadcast network. The switch may further receive a first multicast route through the first controller client; receive a second multicast route through the second controller client; and program at least one of the first multicast route and the second multicast route into a multicast routing information base.

公开(公告)号：US20220417143A1

公开(公告)日：2022-12-29

申请号：US17902158

申请日：2022-09-02

Applicant: Cisco Technology, Inc.

Inventor： Pascal Thubert ,  Eric Levy-Abegnoli ,  Patrick Wetterwald

IPC: H04L45/00 ,  H04L12/46 ,  H04L45/02 ,  H04L49/201

Abstract: Techniques for leveraging MLD capabilities at edge nodes of network fabrics to receive SNMAs from silent hosts, and creating unicast addresses from the SNMAs for the silent nodes that are used as secondary matches in a network overlay if primary unicast address lookups fail. The edge nodes described herein may act as snoopers of MLD reports in order to identify the SNMAs of the silent hosts. The edge nodes then forge unicast addresses for the silent hosts that match with the least three bytes of the SNMAs. The forged unicast addresses are presented as unicast MAC/IP mappings in the fabric overlay. In situations where a primary IP address lookup fails, the look-up device performs a secondary lookup for a mapped address that has the last three bytes of the IP address. If a mapping is found, the lookup is sent as a unicast message to the matching MAC address.

公开(公告)号：US11496329B2

公开(公告)日：2022-11-08

申请号：US16825732

申请日：2020-03-20

Applicant: Juniper Networks, Inc.

Inventor： Vikram Nagarajan ,  Robert W. Kebler ,  Dinesh Sivaraj ,  Vinod Kumar N

IPC: H04L12/18 ,  H04L12/46 ,  H04L45/50 ,  H04L9/40 ,  H04L49/201 ,  H04L47/10 ,  H04L49/10 ,  H04L47/00

Abstract: The techniques describe example network systems providing core-facing designated forwarder (DF) election to forward multicast traffic into an EVPN of a core network. For example, a first PE device of a plurality of PE devices participating in an EVPN comprises one or more processors operably coupled to a memory, wherein the one or more processors are configured to: determine that a first multicast traffic flow has started for the first PE device; in response, send a source-active (SA) route to indicate the first multicast traffic flow has started for the first PE device; receive, from a second PE device, a second SA route that indicates that a second multicast traffic flow has started for the second PE device; and perform an election of a core-facing DF from among the first PE device and second PE device, wherein the core-facing DF is configured to forward the multicast traffic into the EVPN.

公开(公告)号：US11343008B2

公开(公告)日：2022-05-24

申请号：US16983710

申请日：2020-08-03

Applicant: Pulselink, Inc

Inventor： Ivan Krivokapic

IPC: H04J3/08 ,  H04L12/28 ,  H04L49/201 ,  H04J3/16

Abstract: A method of proprietary TDMA (Time-Division Multiple Access) data modulated signals nonlinear signal splitting (switching) system is disclosed. Said TDMA system operates over distribution CATV infrastructure and in ES (extended spectrum) that is usually allocated above in the frequency band comparing to one defined in the CATV DOCSIS standard. Said system is meant to increase data throughput capacity over existing CATV based systems targeting primarily ES (Extended Spectrum band) by means of TDMA approach. The purpose of the RF switches based tap box is to connect specific device to which TDMA packet is relayed to. This approach reduces excessive losses that are present in standard tap boxes by disconnecting other devices, which are not receiving or sending related TDMA data packets. The described method introduces switch control receiver concept that allows for configuration of various operation modes such as regular switched TDMA, amplified and broadcast modes.

公开(公告)号：US11334356B2

公开(公告)日：2022-05-17

申请号：US16457994

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Jian-Guo Chen ,  David T. Dougherty ,  Steven Pinault ,  Parakalan Venkataraghavan ,  Joseph Williams ,  Meng-Lin Yu ,  Kamran Azadet

IPC: G06F9/30 ,  H04L49/25 ,  H04L49/201 ,  G06F9/54

Abstract: Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described. In one embodiment, a processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having fields that identify packed input data, packed control data, and a packed data destination; and an execution unit to execute the decoded single instruction to: send the packed control data to respective control inputs of a circuit that comprises an inverse butterfly circuit coupled in series to a butterfly circuit, wherein the inverse butterfly circuit comprises a first plurality of stages of multicast switches and the butterfly circuit comprises a second plurality of stages of multicast switches, read, once from storage separate from the circuit, each element of the packed input data as respective inputs of the circuit, route the packed input data through the circuit according to the packed control data, and store resultant packed data from the circuit into the packed data destination.