公开(公告)号：US20180341604A1

公开(公告)日：2018-11-29

申请号：US15987663

申请日：2018-05-23

Applicant: THALES

Inventor： Hélène GACHON ,  Norbert VENET

IPC: G06F13/20 ,  G06F13/40 ,  H04B10/80 ,  H05K7/20 ,  G02B6/44 ,  B64G1/66

Abstract: A digital processing device with high input/output connectivity and modular architecture comprises a first plurality of input ports, a second plurality of output ports, and a third plurality of at least four basic elementary modules. The third plurality of the elementary modules is split up according to a partitioning of at least two sub-assemblies of module(s), at least two of which form different islets comprising at least two modules. The digital processing device comprises a harness of optical links for mutually interconnecting the sub-assemblies of modules whose interconnection lengths are compatible with interconnection runs between two interconnected islets which make it possible to avoid, by sidestepping, one or more items of equipment external to the digital processing device, and which are installed on a space platform and interposed between the two interconnected islets, or which make it possible to distribute at least two interconnected islets over two heat exchange zones of the space platform that are far separated by a separation distance on the scale of the size of the platform.

公开(公告)号：US20130094817A1

公开(公告)日：2013-04-18

申请号：US13650795

申请日：2012-10-12

Applicant: THALES

Inventor： Yann OSTER ,  Michel SOTOM ,  Norbert VENET

IPC: G02B6/43

CPC classification number: H03K19/177 ,  H03K19/17736 ,  H03K19/17744

Abstract: A system of one or more integrated circuits is interconnected to a matrix architecture of rows and columns, a row receiving at least one input for signals, and a column providing at least one output for signals, the interconnections between two integrated circuits of a row and the interconnections between two integrated circuits of a column being electrical, and an assembly of at least one integrated circuit comprising at least one input integrated circuit and at least one output integrated circuit, an input integrated circuit being optionally an output integrated circuit, and at least one optical interconnection connecting an input of a row of the system to a respective input of the input integrated circuits of the assemblies, belonging to said row, or for connecting an output of a column of the system to a respective output of the output integrated circuits of the assemblies, belonging to the said column.

Abstract translation: 一个或多个集成电路的系统被互连到行和列的矩阵体系结构，一行接收用于信号的至少一个输入，以及一列提供用于信号的至少一个输出，一行的两个集成电路之间的互连和 柱的两个集成电路之间的互连是电的，以及包括至少一个输入集成电路和至少一个输出集成电路的至少一个集成电路的组件，可选地是输出集成电路的输入集成电路，并且至少 一个光学互连将系统的行的输入连接到属于所述行的组件的输入集成电路的相应输入，或用于将系统的列的输出连接到输出集成电路的相应输出 属于所述列的组件。