公开(公告)号：US20160004534A1

公开(公告)日：2016-01-07

申请号：US14323040

申请日：2014-07-03

Applicant: The Regents Of The University of Michigan

Inventor： Shruti PADMANABHA ,  Andrew LUKEFAHR ,  Reetuparna DAS ,  Scott MAHLKE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30189 ,  G06F1/32 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3891

Abstract: A data processing apparatus 2 includes a first execution mechanism 4, such as an out-of-order processing circuitry, and a second execution mechanism 6 such as an in-order processing circuitry. Switching control circuitry 24 controls switching between which of the first execution circuitry 4 and the second execution circuitry 6 is active at a given time. Latency indicating signals indicative of the latency associated with a candidate switching operation to be performed are supplied to the switching control circuitry 24 and used to control the switching operation. The control of the switching operation may be to accelerate the switching operation, prevent the switching operation, perform early architectural state data transfer or other possibilities.

Abstract translation: 数据处理装置2包括诸如无序处理电路的第一执行机构4和诸如按顺序处理电路的第二执行机构6。 开关控制电路24控制在给定时间在第一执行电路4和第二执行电路6中的哪一个是有效的切换。 指示与要执行的候选切换操作相关联的延迟的延迟指示信号被提供给切换控制电路24，并用于控制切换操作。 切换操作的控制可以是加速切换操作，防止切换操作，执行早期架构状态数据传送或其他可能性。

公开(公告)号：US20180285111A1

公开(公告)日：2018-10-04

申请号：US15478552

申请日：2017-04-04

Applicant: The Regents of the University of Michigan

Inventor： Shruti PADMANABHA ,  Andrew LUKEFAHR ,  Reetuparna DAS ,  Scott MAHLKE

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: A method of detecting repetition of an out-of-order execution schedule for a group of instructions executed by an out-of-order processor, said method comprising: determining data indicative of at least one performance metric for an instance of execution of said group of instructions by said out-of-order processor; performing a comparison of said determined data with previous data of said at least one performance metric for at least one previous instance of execution of said group of instructions by said out-of-order processor; and detecting repetition of said out-of-order execution schedule dependent on said comparison, a corresponding apparatus and non-transitory computer-readable medium.

公开(公告)号：US20170262285A1

公开(公告)日：2017-09-14

申请号：US15063651

申请日：2016-03-08

Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN

Inventor： Andrew LUKEFAHR ,  Shruti PADMANABHA ,  Reetuparna DAS ,  Scott MAHLKE ,  Jiecao YU

IPC: G06F9/30

CPC classification number: G06F9/3834 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3867

Abstract: Apparatus and a corresponding method for controlling a transition between use of first processing circuitry and second processing circuitry to execute program instructions are provided. Transition monitoring storage selects an entry for a load program instruction executed during the transition in dependence on a memory address from which a value is to be loaded and stores a program order timestamp for the load program instruction, unless a valid previously stored program order timestamp in the entry precedes the program order timestamp. Thus the oldest timestamp of an load instruction executed in the transition is held. At either the start or end (or both) of the transition the content of the transition monitoring storage is cleared. When a store program instruction is executed during the transition and when a further program order timestamp for the store program instruction indicates that the store program instruction precedes in program order a load program instruction already executed in the transition, program instructions which follow the store program instruction in the first and second processing circuitry are squashed and re-executed. Data hazards which could otherwise arise during the transition are thus avoided by the use of transition monitoring storage which is nevertheless conveniently small.