公开(公告)号：US09646864B2

公开(公告)日：2017-05-09

申请号：US14055490

申请日：2013-10-16

Applicant: TOKYO ELECTRON LIMITED

Inventor： Daisuke Morisawa

IPC: H01L21/677 ,  H01L21/67

CPC classification number: H01L21/67703 ,  H01L21/67276

Abstract: A substrate processing system includes a plurality of processing chambers configured to perform a predetermined processing with respect to substrates, a transfer device configured to transfer the substrates to the processing chambers in a predetermined order, and a delivery unit configured to deliver the substrates between the delivery unit and the transfer device. The substrate processing system configured to sequentially process the substrates by repeating an operation in a predetermined transfer order. The substrate processing system includes a transfer order setting unit and a transfer control unit configured to switch the first transfer order to the second transfer order.

公开(公告)号：US11101154B2

公开(公告)日：2021-08-24

申请号：US16152812

申请日：2018-10-05

Applicant: TOKYO ELECTRON LIMITED

Inventor： Daisuke Morisawa

IPC: H01L21/67 ,  G05B19/418

Abstract: A method of processing a target substrate includes a process of serially executing multiple processes including a main process and first to M-th subprocesses (where M is a positive integer). An index value indicating one execution of the main process is accumulated for each execution of the main process. The main process is executed multiple times in the process of serially executing multiple processes. An i-th subprocess (where i is a positive integer that satisfies 1≤i≤M) is executed once or multiple times in the process of serially executing multiple processes, and is executed subsequent to one or multiple consecutive executions of the main process. The i-th application and execution conditions are changeable.

公开(公告)号：US10186422B2

公开(公告)日：2019-01-22

申请号：US14060182

申请日：2013-10-22

Applicant: TOKYO ELECTRON LIMITED

Inventor： Naohide Ito ,  Keiji Osada ,  Daisuke Morisawa

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/67

Abstract: A substrate processing apparatus is provided with a process module including a processing container, a rotary table installed within the processing container, the rotary table having a plurality of placing regions to receive substrates, and a process gas supply unit supplying a process gas to the placing regions, a load port in which a transfer container is placed, a dummy substrate receiving unit, a transfer chamber including a transfer mechanism delivering the product substrates or the dummy substrates between the transfer container or the dummy substrate receiving unit and the rotary table, a setting unit setting a placing region to which one of the product substrates is to be transferred, and a control unit outputting a control signal such that the dummy substrates are carried into the remaining placing regions.

公开(公告)号：US09828675B2

公开(公告)日：2017-11-28

申请号：US14860251

申请日：2015-09-21

Applicant: TOKYO ELECTRON LIMITED

Inventor： Naohide Ito ,  Daisuke Morisawa ,  Keiji Osada

IPC: H01L21/31 ,  C23C16/458 ,  H01L21/02 ,  H01L21/67 ,  C23C16/52 ,  H01L21/677

CPC classification number: C23C16/4584 ,  C23C16/52 ,  H01L21/02263 ,  H01L21/67201 ,  H01L21/67745

Abstract: Disclosed is a processing apparatus. The processing apparatus includes: a load port in which a conveyance container accommodating a plurality of semiconductor wafers is placed; a dummy wafer storage area in which a conveyance container accommodating a plurality of dummy wafers is placed; a normal-pressure conveyance room in which a first conveyance arm is installed; an equipment that processes the plurality of semiconductor wafers in a state where the semiconductor wafers and the dummy wafers which are conveyed are placed in slots, respectively; and a controller that controls each component of the processing apparatus. The controller classifies the dummy wafers accommodated in the conveyance container into a plurality of groups, and controls the first conveyance arm to preferentially convey the dummy wafers within one of the classified groups to the equipment and, in replacing the dummy wafers, to perform replacement of the dummy wafers group to group as classified.

公开(公告)号：US09845531B2

公开(公告)日：2017-12-19

申请号：US14455795

申请日：2014-08-08

Applicant: Tokyo Electron Limited

Inventor： Daisuke Morisawa ,  Junichi Ogawa

IPC: C23C16/44 ,  H01L21/67

CPC classification number: C23C16/4401 ,  H01L21/67276

Abstract: A substrate processing system for sequentially processing substrates includes processing chambers, a transfer unit, and a control unit controlling the processing chambers and the transfer unit. The control unit includes a transfer control unit controlling an operation of the transfer unit, a transfer order setting unit setting a transfer order of substrates to the processing chambers, an accumulation unit for accumulating a film thickness of a formed thin film or the number of processed substrates after completion of previous cleaning or previous pre-coating in the processing chambers, a processing chamber priority determination unit for determining priority of processing the substrates in the processing chambers based on predetermined rules, and an execution instruction unit for executing conditioning in the processing chambers. The control unit prevents the substrates from being simultaneously processed in all processing chambers during one cycle of executing conditioning once in each of the processing chambers.